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Fix the instruction of RISC-V arch that yield CPU

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Replace fence with pause in opcode form,
as GCC doesn't support fence operand.
Amends a7f227f56cfe562280e89d3c73040f7e8384129e.
Remove the builtin pause checking,
as in GCC13 this will always pass,
while the opcode pause works
regardless of the pause extension.

Task-number: QTBUG-103014
Change-Id: I26e3c3b9f7d234be24abe1570aaf4c8cb3a272b3
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
(cherry picked from commit 61bd614abea0cbff83595ebf31b0beeccaef5304)
Reviewed-by: Qt Cherry-pick Bot <cherrypick_bot@qt-project.org>
This commit is contained in:
Alex Bu 2024-02-21 14:15:11 +02:00 committed by Qt Cherry-pick Bot
parent 4baeef91d3
commit 684aec428a
1 changed files with 1 additions and 3 deletions
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4
src/corelib/thread/qyieldcpu.h
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@ -51,10 +51,8 @@ void qYieldCpu(void)
#elif defined(Q_PROCESSOR_ARM) && Q_PROCESSOR_ARM >= 7 && defined(Q_CC_GNU)
asm("yield"); // this works everywhere
#elif __has_builtin(__builtin_riscv_pause)
__builtin_riscv_pause(); // Zihintpause extension
#elif defined(Q_PROCESSOR_RISCV)
asm("fence w, 0"); // a.k.a. "pause"
asm(".word 0x0100000f"); // a.k.a. "pause"
#elif defined(_YIELD_PROCESSOR) && defined(Q_CC_GHS)
_YIELD_PROCESSOR; // Green Hills (INTEGRITY), but only on ARM