From 684aec428ab15a50a78a30faec3f640a3dedce04 Mon Sep 17 00:00:00 2001 From: Alex Bu Date: Wed, 21 Feb 2024 14:15:11 +0200 Subject: [PATCH] Fix the instruction of RISC-V arch that yield CPU Replace fence with pause in opcode form, as GCC doesn't support fence operand. Amends a7f227f56cfe562280e89d3c73040f7e8384129e. Remove the builtin pause checking, as in GCC13 this will always pass, while the opcode pause works regardless of the pause extension. Task-number: QTBUG-103014 Change-Id: I26e3c3b9f7d234be24abe1570aaf4c8cb3a272b3 Reviewed-by: Thiago Macieira (cherry picked from commit 61bd614abea0cbff83595ebf31b0beeccaef5304) Reviewed-by: Qt Cherry-pick Bot --- src/corelib/thread/qyieldcpu.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/corelib/thread/qyieldcpu.h b/src/corelib/thread/qyieldcpu.h index db39b2f9e50..d5da58deeb9 100644 --- a/src/corelib/thread/qyieldcpu.h +++ b/src/corelib/thread/qyieldcpu.h @@ -51,10 +51,8 @@ void qYieldCpu(void) #elif defined(Q_PROCESSOR_ARM) && Q_PROCESSOR_ARM >= 7 && defined(Q_CC_GNU) asm("yield"); // this works everywhere -#elif __has_builtin(__builtin_riscv_pause) - __builtin_riscv_pause(); // Zihintpause extension #elif defined(Q_PROCESSOR_RISCV) - asm("fence w, 0"); // a.k.a. "pause" + asm(".word 0x0100000f"); // a.k.a. "pause" #elif defined(_YIELD_PROCESSOR) && defined(Q_CC_GHS) _YIELD_PROCESSOR; // Green Hills (INTEGRITY), but only on ARM