Rename ir.rs to hir.rs to avoid namespace ambiguity with backend

This commit is contained in:
Maxime Chevalier-Boisvert 2025-02-14 14:16:15 -05:00 committed by Takashi Kokubun
parent 22eec65928
commit ce9c9e0a6a
Notes: git 2025-04-18 13:48:38 +00:00
5 changed files with 15 additions and 8 deletions

2
zjit/Cargo.lock generated
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@ -45,7 +45,7 @@ checksum = "0fda2ff0d084019ba4d7c6f371c95d8fd75ce3524c3cb8fb653a3023f6323e64"
[[package]]
name = "zjit"
version = "0.0.0"
version = "0.0.1"
dependencies = [
"capstone",
]

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@ -1,6 +1,6 @@
[package]
name = "zjit"
version = "0.0.0"
version = "0.0.1"
edition = "2021" # Rust 2021 edition to compile with
rust-version = "1.77.0" # Minimally supported rust version
publish = false # Don't publish to crates.io

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@ -1,4 +1,11 @@
use crate::{asm::CodeBlock, backend::*, cruby::*, debug, ir::{self, Function, Insn::*}, virtualmem::CodePtr};
use crate::{
asm::CodeBlock,
backend::*,
cruby::*,
debug,
hir::{self, Function, Insn::*},
virtualmem::CodePtr
};
#[cfg(feature = "disasm")]
use crate::get_option;
@ -55,7 +62,7 @@ fn gen_entry_prologue(asm: &mut Assembler) {
}
/// Compile code that exits from JIT code with a return value
fn gen_return(asm: &mut Assembler, val: ir::Opnd) -> Option<()> {
fn gen_return(asm: &mut Assembler, val: hir::Opnd) -> Option<()> {
// Pop frame: CFP = CFP + RUBY_SIZEOF_CONTROL_FRAME
let incr_cfp = asm.add(CFP, RUBY_SIZEOF_CONTROL_FRAME.into());
asm.mov(CFP, incr_cfp);
@ -71,7 +78,7 @@ fn gen_return(asm: &mut Assembler, val: ir::Opnd) -> Option<()> {
// Return a value
let val = match val {
ir::Opnd::Const(val) => val,
hir::Opnd::Const(val) => val,
_ => return None, // TODO: Support Opnd::Insn
};
asm.cret(val.into());

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@ -3,7 +3,7 @@
mod state;
mod cruby;
mod ir;
mod hir;
mod codegen;
mod stats;
mod cast;
@ -83,7 +83,7 @@ pub extern "C" fn rb_zjit_iseq_gen_entry_point(iseq: IseqPtr, _ec: EcPtr) -> *co
// TODO: acquire the VM barrier
// Compile ISEQ into SSA IR
let ssa = match ir::iseq_to_ssa(iseq) {
let ssa = match hir::iseq_to_ssa(iseq) {
Ok(ssa) => ssa,
Err(err) => {
debug!("ZJIT: to_ssa: {:?}", err);
@ -91,7 +91,7 @@ pub extern "C" fn rb_zjit_iseq_gen_entry_point(iseq: IseqPtr, _ec: EcPtr) -> *co
}
};
// Compile SSA IR into machine code (TODO)
// Compile SSA IR into machine code
let cb = ZJITState::get_code_block();
match gen_function(cb, &ssa) {
Some(start_ptr) => start_ptr.raw_ptr(cb),