Anonymous union is a C11 feature unavailable to us
This commit is contained in:
Alan Wu
parent
e84083593c
commit
beab644408
92
ujit_asm.c
92
ujit_asm.c
@ -43,12 +43,12 @@ size_t unsig_imm_size(uint64_t imm)
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x86opnd_t mem_opnd(size_t num_bits, x86opnd_t base_reg, int32_t disp)
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{
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bool is_iprel = base_reg.reg.reg_type == REG_IP;
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bool is_iprel = base_reg.as.reg.reg_type == REG_IP;
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x86opnd_t opnd = {
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OPND_MEM,
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num_bits,
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.mem = { base_reg.reg.reg_no, 0, 0, false, is_iprel, disp }
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.as.mem = { base_reg.as.reg.reg_no, 0, 0, false, is_iprel, disp }
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};
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return opnd;
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@ -67,7 +67,7 @@ x86opnd_t imm_opnd(int64_t imm)
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x86opnd_t opnd = {
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OPND_IMM,
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sig_imm_size(imm),
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.imm = imm
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.as.imm = imm
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};
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return opnd;
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@ -78,7 +78,7 @@ x86opnd_t const_ptr_opnd(void* ptr)
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x86opnd_t opnd = {
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OPND_IMM,
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64,
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.unsig_imm = (uint64_t)ptr
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.as.unsig_imm = (uint64_t)ptr
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};
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return opnd;
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@ -300,14 +300,14 @@ bool rex_needed(x86opnd_t opnd)
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if (opnd.type == OPND_REG)
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{
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return (
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opnd.reg.reg_no > 7 ||
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(opnd.num_bits == 8 && opnd.reg.reg_no >= 4 && opnd.reg.reg_no <= 7)
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opnd.as.reg.reg_no > 7 ||
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(opnd.num_bits == 8 && opnd.as.reg.reg_no >= 4 && opnd.as.reg.reg_no <= 7)
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);
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}
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if (opnd.type == OPND_MEM)
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{
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return (opnd.mem.base_reg_no > 7) || (opnd.mem.has_idx && opnd.mem.idx_reg_no > 7);
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return (opnd.as.mem.base_reg_no > 7) || (opnd.as.mem.has_idx && opnd.as.mem.idx_reg_no > 7);
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}
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assert (false);
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@ -320,9 +320,9 @@ bool sib_needed(x86opnd_t opnd)
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return false;
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return (
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opnd.mem.has_idx ||
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opnd.mem.base_reg_no == RSP.reg.reg_no ||
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opnd.mem.base_reg_no == R12.reg.reg_no
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opnd.as.mem.has_idx ||
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opnd.as.mem.base_reg_no == RSP.as.reg.reg_no ||
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opnd.as.mem.base_reg_no == R12.as.reg.reg_no
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);
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}
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@ -332,15 +332,15 @@ size_t disp_size(x86opnd_t opnd)
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assert (opnd.type == OPND_MEM);
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// If using RIP as the base, use disp32
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if (opnd.mem.is_iprel)
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if (opnd.as.mem.is_iprel)
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{
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return 32;
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}
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// Compute the required displacement size
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if (opnd.mem.disp != 0)
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if (opnd.as.mem.disp != 0)
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{
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size_t num_bits = sig_imm_size(opnd.mem.disp);
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size_t num_bits = sig_imm_size(opnd.as.mem.disp);
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assert (num_bits <= 32 && "displacement does not fit in 32 bits");
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// x86 can only encode 8-bit and 32-bit displacements
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@ -351,8 +351,8 @@ size_t disp_size(x86opnd_t opnd)
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}
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// If EBP or RBP or R13 is used as the base, displacement must be encoded
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if (opnd.mem.base_reg_no == RBP.reg.reg_no ||
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opnd.mem.base_reg_no == R13.reg.reg_no)
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if (opnd.as.mem.base_reg_no == RBP.as.reg.reg_no ||
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opnd.as.mem.base_reg_no == R13.as.reg.reg_no)
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{
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return 8;
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}
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@ -388,7 +388,7 @@ static void cb_write_rex(
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static void cb_write_opcode(codeblock_t* cb, uint8_t opcode, x86opnd_t reg)
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{
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// Write the reg field into the opcode byte
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uint8_t op_byte = opcode | (reg.reg.reg_no & 7);
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uint8_t op_byte = opcode | (reg.as.reg.reg_no & 7);
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cb_write_byte(cb, op_byte);
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}
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@ -429,21 +429,21 @@ void cb_write_rm(
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uint8_t r;
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if (r_opnd.type != OPND_NONE)
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r = (r_opnd.reg.reg_no & 8)? 1:0;
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r = (r_opnd.as.reg.reg_no & 8)? 1:0;
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else
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r = 0;
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uint8_t x;
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if (need_sib && rm_opnd.mem.has_idx)
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x = (rm_opnd.mem.idx_reg_no & 8)? 1:0;
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if (need_sib && rm_opnd.as.mem.has_idx)
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x = (rm_opnd.as.mem.idx_reg_no & 8)? 1:0;
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else
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x = 0;
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uint8_t b;
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if (rm_opnd.type == OPND_REG)
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b = (rm_opnd.reg.reg_no & 8)? 1:0;
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b = (rm_opnd.as.reg.reg_no & 8)? 1:0;
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else if (rm_opnd.type == OPND_MEM)
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b = (rm_opnd.mem.base_reg_no & 8)? 1:0;
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b = (rm_opnd.as.mem.base_reg_no & 8)? 1:0;
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else
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b = 0;
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@ -480,7 +480,7 @@ void cb_write_rm(
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else
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{
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size_t dsize = disp_size(rm_opnd);
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if (dsize == 0 || rm_opnd.mem.is_iprel)
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if (dsize == 0 || rm_opnd.as.mem.is_iprel)
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mod = 0;
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else if (dsize == 8)
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mod = 1;
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@ -495,7 +495,7 @@ void cb_write_rm(
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if (opExt != 0xFF)
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reg = opExt;
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else if (r_opnd.type == OPND_REG)
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reg = r_opnd.reg.reg_no & 7;
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reg = r_opnd.as.reg.reg_no & 7;
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else
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reg = 0;
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@ -503,14 +503,14 @@ void cb_write_rm(
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uint8_t rm;
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if (rm_opnd.type == OPND_REG)
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{
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rm = rm_opnd.reg.reg_no & 7;
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rm = rm_opnd.as.reg.reg_no & 7;
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}
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else
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{
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if (need_sib)
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rm = 4;
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else
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rm = rm_opnd.mem.base_reg_no & 7;
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rm = rm_opnd.as.mem.base_reg_no & 7;
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}
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// Encode and write the ModR/M byte
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@ -527,17 +527,17 @@ void cb_write_rm(
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assert (rm_opnd.type == OPND_MEM);
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// Encode the scale value
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uint8_t scale = rm_opnd.mem.scale_exp;
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uint8_t scale = rm_opnd.as.mem.scale_exp;
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// Encode the index value
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uint8_t index;
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if (!rm_opnd.mem.has_idx)
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if (!rm_opnd.as.mem.has_idx)
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index = 4;
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else
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index = rm_opnd.mem.idx_reg_no & 7;
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index = rm_opnd.as.mem.idx_reg_no & 7;
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// Encode the base register
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uint8_t base = rm_opnd.mem.base_reg_no & 7;
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uint8_t base = rm_opnd.as.mem.base_reg_no & 7;
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// Encode and write the SIB byte
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uint8_t sib_byte = (scale << 6) + (index << 3) + (base);
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@ -549,7 +549,7 @@ void cb_write_rm(
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{
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size_t dsize = disp_size(rm_opnd);
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if (dsize > 0)
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cb_write_int(cb, rm_opnd.mem.disp, dsize);
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cb_write_int(cb, rm_opnd.as.mem.disp, dsize);
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}
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}
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@ -656,7 +656,7 @@ void cb_write_rm_multi(
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else
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cb_write_rm(cb, szPref, rexW, NO_OPND, opnd0, opExtImm, 1, opMemImmSml);
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cb_write_int(cb, opnd1.imm, 8);
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cb_write_int(cb, opnd1.as.imm, 8);
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}
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// 32-bit immediate
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@ -664,7 +664,7 @@ void cb_write_rm_multi(
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{
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assert (opnd1.num_bits <= opndSize && "immediate too large for dst");
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cb_write_rm(cb, szPref, rexW, NO_OPND, opnd0, opExtImm, 1, opMemImmLrg);
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cb_write_int(cb, opnd1.imm, (opndSize > 32)? 32:opndSize);
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cb_write_int(cb, opnd1.as.imm, (opndSize > 32)? 32:opndSize);
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}
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// Immediate too large
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@ -708,7 +708,7 @@ void cb_write_shift(
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if (opnd1.type == OPND_IMM)
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{
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if (opnd1.imm == 1)
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if (opnd1.as.imm == 1)
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{
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cb_write_rm(cb, szPref, rexW, NO_OPND, opnd0, opExt, 1, opMemOnePref);
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}
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@ -716,7 +716,7 @@ void cb_write_shift(
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{
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assert (opnd1.num_bits <= 8);
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cb_write_rm(cb, szPref, rexW, NO_OPND, opnd0, opExt, 1, opMemImmPref);
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cb_write_byte(cb, (uint8_t)opnd1.imm);
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cb_write_byte(cb, (uint8_t)opnd1.as.imm);
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}
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}
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/*
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@ -1109,17 +1109,17 @@ void mov(codeblock_t* cb, x86opnd_t dst, x86opnd_t src)
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{
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assert (
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src.num_bits <= dst.num_bits ||
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unsig_imm_size(src.imm) <= dst.num_bits
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unsig_imm_size(src.as.imm) <= dst.num_bits
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);
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if (dst.num_bits == 16)
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cb_write_byte(cb, 0x66);
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if (rex_needed(dst) || dst.num_bits == 64)
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cb_write_rex(cb, dst.num_bits == 64, 0, 0, dst.reg.reg_no);
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cb_write_rex(cb, dst.num_bits == 64, 0, 0, dst.as.reg.reg_no);
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cb_write_opcode(cb, (dst.num_bits == 8)? 0xB0:0xB8, dst);
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cb_write_int(cb, src.imm, dst.num_bits);
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cb_write_int(cb, src.as.imm, dst.num_bits);
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}
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// M + Imm
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@ -1132,7 +1132,7 @@ void mov(codeblock_t* cb, x86opnd_t dst, x86opnd_t src)
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else
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cb_write_rm(cb, dst.num_bits == 16, dst.num_bits == 64, NO_OPND, dst, 0, 1, 0xC7);
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cb_write_int(cb, src.imm, (dst.num_bits > 32)? 32:dst.num_bits);
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cb_write_int(cb, src.as.imm, (dst.num_bits > 32)? 32:dst.num_bits);
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}
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else
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@ -1346,7 +1346,7 @@ void pop(codeblock_t* cb, x86opnd_t reg)
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//cb.writeASM("pop", reg);
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if (rex_needed(reg))
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cb_write_rex(cb, false, 0, 0, reg.reg.reg_no);
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cb_write_rex(cb, false, 0, 0, reg.as.reg.reg_no);
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cb_write_opcode(cb, 0x58, reg);
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}
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@ -1368,7 +1368,7 @@ void push(codeblock_t* cb, x86opnd_t reg)
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//cb.writeASM("push", reg);
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if (rex_needed(reg))
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cb_write_rex(cb, false, 0, 0, reg.reg.reg_no);
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cb_write_rex(cb, false, 0, 0, reg.as.reg.reg_no);
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cb_write_opcode(cb, 0x50, reg);
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}
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@ -1470,22 +1470,22 @@ void test(codeblock_t* cb, x86opnd_t rm_opnd, x86opnd_t imm_opnd)
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{
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assert (rm_opnd.type == OPND_REG || rm_opnd.type == OPND_MEM);
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assert (imm_opnd.type == OPND_IMM);
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assert (imm_opnd.imm >= 0);
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assert (unsig_imm_size(imm_opnd.unsig_imm) <= 32);
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assert (unsig_imm_size(imm_opnd.unsig_imm) <= rm_opnd.num_bits);
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assert (imm_opnd.as.imm >= 0);
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assert (unsig_imm_size(imm_opnd.as.unsig_imm) <= 32);
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assert (unsig_imm_size(imm_opnd.as.unsig_imm) <= rm_opnd.num_bits);
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// Use the smallest operand size possible
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rm_opnd = resize_opnd(rm_opnd, unsig_imm_size(imm_opnd.unsig_imm));
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rm_opnd = resize_opnd(rm_opnd, unsig_imm_size(imm_opnd.as.unsig_imm));
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if (rm_opnd.num_bits == 8)
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{
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cb_write_rm(cb, false, false, NO_OPND, rm_opnd, 0x00, 1, 0xF6);
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cb_write_int(cb, imm_opnd.imm, rm_opnd.num_bits);
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cb_write_int(cb, imm_opnd.as.imm, rm_opnd.num_bits);
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}
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else
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{
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cb_write_rm(cb, rm_opnd.num_bits == 16, false, NO_OPND, rm_opnd, 0x00, 1, 0xF7);
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cb_write_int(cb, imm_opnd.imm, rm_opnd.num_bits);
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cb_write_int(cb, imm_opnd.as.imm, rm_opnd.num_bits);
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}
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}
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134
ujit_asm.h
134
ujit_asm.h
@ -127,87 +127,87 @@ typedef struct X86Opnd
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// Unsigned immediate value
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uint64_t unsig_imm;
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};
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} as;
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} x86opnd_t;
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// Dummy none/null operand
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static const x86opnd_t NO_OPND = { OPND_NONE, 0, .imm = 0 };
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static const x86opnd_t NO_OPND = { OPND_NONE, 0, .as.imm = 0 };
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// Instruction pointer
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static const x86opnd_t RIP = { OPND_REG, 64, .reg = { REG_IP, 5 }};
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static const x86opnd_t RIP = { OPND_REG, 64, .as.reg = { REG_IP, 5 }};
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// 64-bit GP registers
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static const x86opnd_t RAX = { OPND_REG, 64, .reg = { REG_GP, 0 }};
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static const x86opnd_t RCX = { OPND_REG, 64, .reg = { REG_GP, 1 }};
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static const x86opnd_t RDX = { OPND_REG, 64, .reg = { REG_GP, 2 }};
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static const x86opnd_t RBX = { OPND_REG, 64, .reg = { REG_GP, 3 }};
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static const x86opnd_t RSP = { OPND_REG, 64, .reg = { REG_GP, 4 }};
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static const x86opnd_t RBP = { OPND_REG, 64, .reg = { REG_GP, 5 }};
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static const x86opnd_t RSI = { OPND_REG, 64, .reg = { REG_GP, 6 }};
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static const x86opnd_t RDI = { OPND_REG, 64, .reg = { REG_GP, 7 }};
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static const x86opnd_t R8 = { OPND_REG, 64, .reg = { REG_GP, 8 }};
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static const x86opnd_t R9 = { OPND_REG, 64, .reg = { REG_GP, 9 }};
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static const x86opnd_t R10 = { OPND_REG, 64, .reg = { REG_GP, 10 }};
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static const x86opnd_t R11 = { OPND_REG, 64, .reg = { REG_GP, 11 }};
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static const x86opnd_t R12 = { OPND_REG, 64, .reg = { REG_GP, 12 }};
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static const x86opnd_t R13 = { OPND_REG, 64, .reg = { REG_GP, 13 }};
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static const x86opnd_t R14 = { OPND_REG, 64, .reg = { REG_GP, 14 }};
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static const x86opnd_t R15 = { OPND_REG, 64, .reg = { REG_GP, 15 }};
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static const x86opnd_t RAX = { OPND_REG, 64, .as.reg = { REG_GP, 0 }};
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static const x86opnd_t RCX = { OPND_REG, 64, .as.reg = { REG_GP, 1 }};
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static const x86opnd_t RDX = { OPND_REG, 64, .as.reg = { REG_GP, 2 }};
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static const x86opnd_t RBX = { OPND_REG, 64, .as.reg = { REG_GP, 3 }};
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static const x86opnd_t RSP = { OPND_REG, 64, .as.reg = { REG_GP, 4 }};
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static const x86opnd_t RBP = { OPND_REG, 64, .as.reg = { REG_GP, 5 }};
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static const x86opnd_t RSI = { OPND_REG, 64, .as.reg = { REG_GP, 6 }};
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static const x86opnd_t RDI = { OPND_REG, 64, .as.reg = { REG_GP, 7 }};
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static const x86opnd_t R8 = { OPND_REG, 64, .as.reg = { REG_GP, 8 }};
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static const x86opnd_t R9 = { OPND_REG, 64, .as.reg = { REG_GP, 9 }};
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static const x86opnd_t R10 = { OPND_REG, 64, .as.reg = { REG_GP, 10 }};
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static const x86opnd_t R11 = { OPND_REG, 64, .as.reg = { REG_GP, 11 }};
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static const x86opnd_t R12 = { OPND_REG, 64, .as.reg = { REG_GP, 12 }};
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static const x86opnd_t R13 = { OPND_REG, 64, .as.reg = { REG_GP, 13 }};
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static const x86opnd_t R14 = { OPND_REG, 64, .as.reg = { REG_GP, 14 }};
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static const x86opnd_t R15 = { OPND_REG, 64, .as.reg = { REG_GP, 15 }};
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// 32-bit GP registers
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static const x86opnd_t EAX = { OPND_REG, 32, .reg = { REG_GP, 0 }};
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static const x86opnd_t ECX = { OPND_REG, 32, .reg = { REG_GP, 1 }};
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static const x86opnd_t EDX = { OPND_REG, 32, .reg = { REG_GP, 2 }};
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static const x86opnd_t EBX = { OPND_REG, 32, .reg = { REG_GP, 3 }};
|
||||
static const x86opnd_t ESP = { OPND_REG, 32, .reg = { REG_GP, 4 }};
|
||||
static const x86opnd_t EBP = { OPND_REG, 32, .reg = { REG_GP, 5 }};
|
||||
static const x86opnd_t ESI = { OPND_REG, 32, .reg = { REG_GP, 6 }};
|
||||
static const x86opnd_t EDI = { OPND_REG, 32, .reg = { REG_GP, 7 }};
|
||||
static const x86opnd_t R8D = { OPND_REG, 32, .reg = { REG_GP, 8 }};
|
||||
static const x86opnd_t R9D = { OPND_REG, 32, .reg = { REG_GP, 9 }};
|
||||
static const x86opnd_t R10D = { OPND_REG, 32, .reg = { REG_GP, 10 }};
|
||||
static const x86opnd_t R11D = { OPND_REG, 32, .reg = { REG_GP, 11 }};
|
||||
static const x86opnd_t R12D = { OPND_REG, 32, .reg = { REG_GP, 12 }};
|
||||
static const x86opnd_t R13D = { OPND_REG, 32, .reg = { REG_GP, 13 }};
|
||||
static const x86opnd_t R14D = { OPND_REG, 32, .reg = { REG_GP, 14 }};
|
||||
static const x86opnd_t R15D = { OPND_REG, 32, .reg = { REG_GP, 15 }};
|
||||
static const x86opnd_t EAX = { OPND_REG, 32, .as.reg = { REG_GP, 0 }};
|
||||
static const x86opnd_t ECX = { OPND_REG, 32, .as.reg = { REG_GP, 1 }};
|
||||
static const x86opnd_t EDX = { OPND_REG, 32, .as.reg = { REG_GP, 2 }};
|
||||
static const x86opnd_t EBX = { OPND_REG, 32, .as.reg = { REG_GP, 3 }};
|
||||
static const x86opnd_t ESP = { OPND_REG, 32, .as.reg = { REG_GP, 4 }};
|
||||
static const x86opnd_t EBP = { OPND_REG, 32, .as.reg = { REG_GP, 5 }};
|
||||
static const x86opnd_t ESI = { OPND_REG, 32, .as.reg = { REG_GP, 6 }};
|
||||
static const x86opnd_t EDI = { OPND_REG, 32, .as.reg = { REG_GP, 7 }};
|
||||
static const x86opnd_t R8D = { OPND_REG, 32, .as.reg = { REG_GP, 8 }};
|
||||
static const x86opnd_t R9D = { OPND_REG, 32, .as.reg = { REG_GP, 9 }};
|
||||
static const x86opnd_t R10D = { OPND_REG, 32, .as.reg = { REG_GP, 10 }};
|
||||
static const x86opnd_t R11D = { OPND_REG, 32, .as.reg = { REG_GP, 11 }};
|
||||
static const x86opnd_t R12D = { OPND_REG, 32, .as.reg = { REG_GP, 12 }};
|
||||
static const x86opnd_t R13D = { OPND_REG, 32, .as.reg = { REG_GP, 13 }};
|
||||
static const x86opnd_t R14D = { OPND_REG, 32, .as.reg = { REG_GP, 14 }};
|
||||
static const x86opnd_t R15D = { OPND_REG, 32, .as.reg = { REG_GP, 15 }};
|
||||
|
||||
// 16-bit GP registers
|
||||
static const x86opnd_t AX = { OPND_REG, 16, .reg = { REG_GP, 0 }};
|
||||
static const x86opnd_t CX = { OPND_REG, 16, .reg = { REG_GP, 1 }};
|
||||
static const x86opnd_t DX = { OPND_REG, 16, .reg = { REG_GP, 2 }};
|
||||
static const x86opnd_t BX = { OPND_REG, 16, .reg = { REG_GP, 3 }};
|
||||
static const x86opnd_t SP = { OPND_REG, 16, .reg = { REG_GP, 4 }};
|
||||
static const x86opnd_t BP = { OPND_REG, 16, .reg = { REG_GP, 5 }};
|
||||
static const x86opnd_t SI = { OPND_REG, 16, .reg = { REG_GP, 6 }};
|
||||
static const x86opnd_t DI = { OPND_REG, 16, .reg = { REG_GP, 7 }};
|
||||
static const x86opnd_t R8W = { OPND_REG, 16, .reg = { REG_GP, 8 }};
|
||||
static const x86opnd_t R9W = { OPND_REG, 16, .reg = { REG_GP, 9 }};
|
||||
static const x86opnd_t R10W = { OPND_REG, 16, .reg = { REG_GP, 10 }};
|
||||
static const x86opnd_t R11W = { OPND_REG, 16, .reg = { REG_GP, 11 }};
|
||||
static const x86opnd_t R12W = { OPND_REG, 16, .reg = { REG_GP, 12 }};
|
||||
static const x86opnd_t R13W = { OPND_REG, 16, .reg = { REG_GP, 13 }};
|
||||
static const x86opnd_t R14W = { OPND_REG, 16, .reg = { REG_GP, 14 }};
|
||||
static const x86opnd_t R15W = { OPND_REG, 16, .reg = { REG_GP, 15 }};
|
||||
static const x86opnd_t AX = { OPND_REG, 16, .as.reg = { REG_GP, 0 }};
|
||||
static const x86opnd_t CX = { OPND_REG, 16, .as.reg = { REG_GP, 1 }};
|
||||
static const x86opnd_t DX = { OPND_REG, 16, .as.reg = { REG_GP, 2 }};
|
||||
static const x86opnd_t BX = { OPND_REG, 16, .as.reg = { REG_GP, 3 }};
|
||||
static const x86opnd_t SP = { OPND_REG, 16, .as.reg = { REG_GP, 4 }};
|
||||
static const x86opnd_t BP = { OPND_REG, 16, .as.reg = { REG_GP, 5 }};
|
||||
static const x86opnd_t SI = { OPND_REG, 16, .as.reg = { REG_GP, 6 }};
|
||||
static const x86opnd_t DI = { OPND_REG, 16, .as.reg = { REG_GP, 7 }};
|
||||
static const x86opnd_t R8W = { OPND_REG, 16, .as.reg = { REG_GP, 8 }};
|
||||
static const x86opnd_t R9W = { OPND_REG, 16, .as.reg = { REG_GP, 9 }};
|
||||
static const x86opnd_t R10W = { OPND_REG, 16, .as.reg = { REG_GP, 10 }};
|
||||
static const x86opnd_t R11W = { OPND_REG, 16, .as.reg = { REG_GP, 11 }};
|
||||
static const x86opnd_t R12W = { OPND_REG, 16, .as.reg = { REG_GP, 12 }};
|
||||
static const x86opnd_t R13W = { OPND_REG, 16, .as.reg = { REG_GP, 13 }};
|
||||
static const x86opnd_t R14W = { OPND_REG, 16, .as.reg = { REG_GP, 14 }};
|
||||
static const x86opnd_t R15W = { OPND_REG, 16, .as.reg = { REG_GP, 15 }};
|
||||
|
||||
// 8-bit GP registers
|
||||
static const x86opnd_t AL = { OPND_REG, 8, .reg = { REG_GP, 0 }};
|
||||
static const x86opnd_t CL = { OPND_REG, 8, .reg = { REG_GP, 1 }};
|
||||
static const x86opnd_t DL = { OPND_REG, 8, .reg = { REG_GP, 2 }};
|
||||
static const x86opnd_t BL = { OPND_REG, 8, .reg = { REG_GP, 3 }};
|
||||
static const x86opnd_t SPL = { OPND_REG, 8, .reg = { REG_GP, 4 }};
|
||||
static const x86opnd_t BPL = { OPND_REG, 8, .reg = { REG_GP, 5 }};
|
||||
static const x86opnd_t SIL = { OPND_REG, 8, .reg = { REG_GP, 6 }};
|
||||
static const x86opnd_t DIL = { OPND_REG, 8, .reg = { REG_GP, 7 }};
|
||||
static const x86opnd_t R8B = { OPND_REG, 8, .reg = { REG_GP, 8 }};
|
||||
static const x86opnd_t R9B = { OPND_REG, 8, .reg = { REG_GP, 9 }};
|
||||
static const x86opnd_t R10B = { OPND_REG, 8, .reg = { REG_GP, 10 }};
|
||||
static const x86opnd_t R11B = { OPND_REG, 8, .reg = { REG_GP, 11 }};
|
||||
static const x86opnd_t R12B = { OPND_REG, 8, .reg = { REG_GP, 12 }};
|
||||
static const x86opnd_t R13B = { OPND_REG, 8, .reg = { REG_GP, 13 }};
|
||||
static const x86opnd_t R14B = { OPND_REG, 8, .reg = { REG_GP, 14 }};
|
||||
static const x86opnd_t R15B = { OPND_REG, 8, .reg = { REG_GP, 15 }};
|
||||
static const x86opnd_t AL = { OPND_REG, 8, .as.reg = { REG_GP, 0 }};
|
||||
static const x86opnd_t CL = { OPND_REG, 8, .as.reg = { REG_GP, 1 }};
|
||||
static const x86opnd_t DL = { OPND_REG, 8, .as.reg = { REG_GP, 2 }};
|
||||
static const x86opnd_t BL = { OPND_REG, 8, .as.reg = { REG_GP, 3 }};
|
||||
static const x86opnd_t SPL = { OPND_REG, 8, .as.reg = { REG_GP, 4 }};
|
||||
static const x86opnd_t BPL = { OPND_REG, 8, .as.reg = { REG_GP, 5 }};
|
||||
static const x86opnd_t SIL = { OPND_REG, 8, .as.reg = { REG_GP, 6 }};
|
||||
static const x86opnd_t DIL = { OPND_REG, 8, .as.reg = { REG_GP, 7 }};
|
||||
static const x86opnd_t R8B = { OPND_REG, 8, .as.reg = { REG_GP, 8 }};
|
||||
static const x86opnd_t R9B = { OPND_REG, 8, .as.reg = { REG_GP, 9 }};
|
||||
static const x86opnd_t R10B = { OPND_REG, 8, .as.reg = { REG_GP, 10 }};
|
||||
static const x86opnd_t R11B = { OPND_REG, 8, .as.reg = { REG_GP, 11 }};
|
||||
static const x86opnd_t R12B = { OPND_REG, 8, .as.reg = { REG_GP, 12 }};
|
||||
static const x86opnd_t R13B = { OPND_REG, 8, .as.reg = { REG_GP, 13 }};
|
||||
static const x86opnd_t R14B = { OPND_REG, 8, .as.reg = { REG_GP, 14 }};
|
||||
static const x86opnd_t R15B = { OPND_REG, 8, .as.reg = { REG_GP, 15 }};
|
||||
|
||||
// Memory operand with base register and displacement/offset
|
||||
x86opnd_t mem_opnd(size_t num_bits, x86opnd_t base_reg, int32_t disp);
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user