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Fixed indents in recently RJIT patch (#11001)

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Dmitry Ukolov 2024-06-14 11:05:21 +04:00 committed by GitHub
parent 2e59cf00cc
commit 8ddb4de0ac
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1 changed files with 20 additions and 20 deletions
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40
lib/ruby_vm/rjit/assembler.rb
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@ -152,16 +152,16 @@ module RubyVM::RJIT
mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg], mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg],
disp: imm8(src_disp), disp: imm8(src_disp),
) )
# AND r64, r/m64 (Mod 10: [reg]+disp32) # AND r64, r/m64 (Mod 10: [reg]+disp32)
in [R64 => dst_reg, QwordPtr[R64 => src_reg, IMM32 => src_disp]] in [R64 => dst_reg, QwordPtr[R64 => src_reg, IMM32 => src_disp]]
# REX.W + 23 /r # REX.W + 23 /r
# RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r) # RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
insn( insn(
prefix: REX_W, prefix: REX_W,
opcode: 0x23, opcode: 0x23,
mod_rm: ModRM[mod: Mod10, reg: dst_reg, rm: src_reg], mod_rm: ModRM[mod: Mod10, reg: dst_reg, rm: src_reg],
disp: imm32(src_disp), disp: imm32(src_disp),
) )
end end
end end
@ -746,16 +746,16 @@ module RubyVM::RJIT
mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg], mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg],
disp: imm8(src_disp), disp: imm8(src_disp),
) )
# OR r64, r/m64 (Mod 10: [reg]+disp32) # OR r64, r/m64 (Mod 10: [reg]+disp32)
in [R64 => dst_reg, QwordPtr[R64 => src_reg, IMM32 => src_disp]] in [R64 => dst_reg, QwordPtr[R64 => src_reg, IMM32 => src_disp]]
# REX.W + 0B /r # REX.W + 0B /r
# RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r) # RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
insn( insn(
prefix: REX_W, prefix: REX_W,
opcode: 0x0b, opcode: 0x0b,
mod_rm: ModRM[mod: Mod10, reg: dst_reg, rm: src_reg], mod_rm: ModRM[mod: Mod10, reg: dst_reg, rm: src_reg],
disp: imm32(src_disp), disp: imm32(src_disp),
) )
end end
end end