Change push insn macros
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@ -399,6 +399,9 @@ impl Assembler
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// Register allocation
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// Generic lowering pass
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// Platform-specific lowering
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// Question: should this method return machine code?
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// How do we go from lowered/optimized insn to an array of bytes?
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}
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}
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@ -410,18 +413,6 @@ impl Assembler
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self.push_insn(Op::Add, vec![ Opnd::String(text.to_owned()) ], None);
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}
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// Low-level, no output operand
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fn test(&mut self, opnd0: Opnd, opnd1: Opnd)
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{
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self.push_insn(Op::Add, vec![opnd0, opnd1], None);
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}
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// Low-level, no output operand
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fn mov(&mut self, opnd0: Opnd, opnd1: Opnd)
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{
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self.push_insn(Op::Add, vec![opnd0, opnd1], None);
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}
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// Jump if not zero
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fn jnz(&mut self, target: Target)
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{
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@ -429,7 +420,7 @@ impl Assembler
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}
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}
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macro_rules! def_push_insn_2_opnd {
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macro_rules! def_push_2_opnd {
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($op_name:ident, $opcode:expr) => {
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impl Assembler
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{
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@ -441,9 +432,23 @@ macro_rules! def_push_insn_2_opnd {
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};
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}
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def_push_insn_2_opnd!(add, Op::Add);
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def_push_insn_2_opnd!(sub, Op::Sub);
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def_push_insn_2_opnd!(and, Op::And);
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macro_rules! def_push_2_opnd_no_out {
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($op_name:ident, $opcode:expr) => {
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impl Assembler
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{
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fn $op_name(&mut self, opnd0: Opnd, opnd1: Opnd)
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{
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self.push_insn($opcode, vec![opnd0, opnd1], None);
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}
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}
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};
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}
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def_push_2_opnd!(add, Op::Add);
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def_push_2_opnd!(sub, Op::Sub);
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def_push_2_opnd!(and, Op::And);
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def_push_2_opnd_no_out!(test, Op::Test);
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def_push_2_opnd_no_out!(mov, Op::Mov);
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// NOTE: these methods are temporary and will likely move
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// to context.rs later
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