cf63b0e1df
This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
99 lines
2.3 KiB
C++
99 lines
2.3 KiB
C++
// This is a generated file. DO NOT EDIT.
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// Please see util/x86simdgen/generate.pl
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#include <qglobal.h>
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static const char features_string[] =
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" sse2\0"
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" sse3\0"
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" ssse3\0"
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" fma\0"
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" sse4.1\0"
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" sse4.2\0"
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" movbe\0"
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" popcnt\0"
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" aes\0"
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" avx\0"
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" f16c\0"
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" rdrnd\0"
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" bmi\0"
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" hle\0"
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" avx2\0"
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" bmi2\0"
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" rtm\0"
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" avx512f\0"
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" avx512dq\0"
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" rdseed\0"
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" avx512ifma\0"
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" avx512pf\0"
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" avx512er\0"
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" avx512cd\0"
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" sha\0"
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" avx512bw\0"
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" avx512vl\0"
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" avx512vbmi\0"
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" avx512vbmi2\0"
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" gfni\0"
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" vaes\0"
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" avx512vnni\0"
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" avx512bitalg\0"
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" avx512vpopcntdq\0"
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" avx5124nniw\0"
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" avx5124fmaps\0"
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"\0";
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static const quint16 features_indices[] = {
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306, 0, 6, 12, 19, 24, 32, 40,
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47, 55, 60, 65, 71, 78, 83, 88,
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94, 100, 105, 114, 124, 132, 144, 154,
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164, 174, 179, 189, 199, 211, 224, 230,
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236, 248, 262, 279, 292
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};
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enum X86CpuidLeaves {
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Leaf1ECX,
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Leaf1EDX,
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Leaf7_0EBX,
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Leaf7_0ECX,
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Leaf7_0EDX,
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X86CpuidMaxLeaf
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};
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static const quint8 x86_locators[] = {
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Leaf1EDX*32 + 26, // sse2
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Leaf1ECX*32 + 0, // sse3
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Leaf1ECX*32 + 9, // ssse3
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Leaf1ECX*32 + 12, // fma
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Leaf1ECX*32 + 19, // sse4.1
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Leaf1ECX*32 + 20, // sse4.2
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Leaf1ECX*32 + 22, // movbe
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Leaf1ECX*32 + 23, // popcnt
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Leaf1ECX*32 + 25, // aes
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Leaf1ECX*32 + 28, // avx
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Leaf1ECX*32 + 29, // f16c
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Leaf1ECX*32 + 30, // rdrnd
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Leaf7_0EBX*32 + 3, // bmi
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Leaf7_0EBX*32 + 4, // hle
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Leaf7_0EBX*32 + 5, // avx2
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Leaf7_0EBX*32 + 8, // bmi2
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Leaf7_0EBX*32 + 11, // rtm
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Leaf7_0EBX*32 + 16, // avx512f
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Leaf7_0EBX*32 + 17, // avx512dq
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Leaf7_0EBX*32 + 18, // rdseed
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Leaf7_0EBX*32 + 21, // avx512ifma
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Leaf7_0EBX*32 + 26, // avx512pf
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Leaf7_0EBX*32 + 27, // avx512er
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Leaf7_0EBX*32 + 28, // avx512cd
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Leaf7_0EBX*32 + 29, // sha
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Leaf7_0EBX*32 + 30, // avx512bw
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Leaf7_0EBX*32 + 31, // avx512vl
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Leaf7_0ECX*32 + 1, // avx512vbmi
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Leaf7_0ECX*32 + 6, // avx512vbmi2
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Leaf7_0ECX*32 + 8, // gfni
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Leaf7_0ECX*32 + 9, // vaes
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Leaf7_0ECX*32 + 11, // avx512vnni
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Leaf7_0ECX*32 + 12, // avx512bitalg
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Leaf7_0ECX*32 + 14, // avx512vpopcntdq
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Leaf7_0EDX*32 + 2, // avx5124nniw
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Leaf7_0EDX*32 + 3 // avx5124fmaps
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};
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