0e100a4d89
Emscripten only supports SSE1, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, and 128-bit AVX instruction sets at this time. https://emscripten.org/docs/porting/simd.html Browsers might need to enable simd support in the advanced configurations about: config or chrome:flags Enable by configuring Qt with -sse2 Pick-to: 6.2 Fixes: QTBUG-63924 Change-Id: Ifeafae20e199dee0d19689802ad20fd0bd424ca7 Reviewed-by: Morten Johan Sørvig <morten.sorvig@qt.io>
417 lines
15 KiB
C
417 lines
15 KiB
C
/****************************************************************************
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**
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** Copyright (C) 2016 The Qt Company Ltd.
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** Copyright (C) 2018 Intel Corporation.
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** Contact: https://www.qt.io/licensing/
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**
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** This file is part of the QtCore module of the Qt Toolkit.
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**
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** $QT_BEGIN_LICENSE:LGPL$
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** Commercial License Usage
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** Licensees holding valid commercial Qt licenses may use this file in
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** accordance with the commercial license agreement provided with the
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** Software or, alternatively, in accordance with the terms contained in
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** a written agreement between you and The Qt Company. For licensing terms
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** and conditions see https://www.qt.io/terms-conditions. For further
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** information use the contact form at https://www.qt.io/contact-us.
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**
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** GNU Lesser General Public License Usage
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** Alternatively, this file may be used under the terms of the GNU Lesser
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** General Public License version 3 as published by the Free Software
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** Foundation and appearing in the file LICENSE.LGPL3 included in the
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** packaging of this file. Please review the following information to
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** ensure the GNU Lesser General Public License version 3 requirements
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** will be met: https://www.gnu.org/licenses/lgpl-3.0.html.
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**
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** GNU General Public License Usage
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** Alternatively, this file may be used under the terms of the GNU
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** General Public License version 2.0 or (at your option) the GNU General
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** Public license version 3 or any later version approved by the KDE Free
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** Qt Foundation. The licenses are as published by the Free Software
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** Foundation and appearing in the file LICENSE.GPL2 and LICENSE.GPL3
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** included in the packaging of this file. Please review the following
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** information to ensure the GNU General Public License requirements will
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** be met: https://www.gnu.org/licenses/gpl-2.0.html and
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** https://www.gnu.org/licenses/gpl-3.0.html.
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**
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** $QT_END_LICENSE$
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**
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****************************************************************************/
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#ifndef QSIMD_P_H
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#define QSIMD_P_H
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//
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// W A R N I N G
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// -------------
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//
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// This file is not part of the Qt API. It exists purely as an
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// implementation detail. This header file may change from version to
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// version without notice, or even be removed.
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//
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// We mean it.
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//
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#include <QtCore/private/qglobal_p.h>
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#include <QtCore/qsimd.h>
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/*
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* qt_module_config.prf defines the QT_COMPILER_SUPPORTS_XXX macros.
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* They mean the compiler supports the necessary flags and the headers
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* for the x86 and ARM intrinsics:
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* - GCC: the -mXXX or march=YYY flag is necessary before #include
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* up to 4.8; GCC >= 4.9 can include unconditionally
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* - Intel CC: #include can happen unconditionally
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* - MSVC: #include can happen unconditionally
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* - RVCT: ???
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*
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* We will try to include all headers possible under this configuration.
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*
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* MSVC does not define __SSE2__ & family, so we will define them. MSVC 2013 &
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* up do define __AVX__ if the -arch:AVX option is passed on the command-line.
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*
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* Supported XXX are:
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* Flag | Arch | GCC | Intel CC | MSVC |
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* ARM_NEON | ARM | I & C | None | ? |
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* SSE2 | x86 | I & C | I & C | I & C |
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* SSE3 | x86 | I & C | I & C | I only |
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* SSSE3 | x86 | I & C | I & C | I only |
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* SSE4_1 | x86 | I & C | I & C | I only |
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* SSE4_2 | x86 | I & C | I & C | I only |
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* AVX | x86 | I & C | I & C | I & C |
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* AVX2 | x86 | I & C | I & C | I only |
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* AVX512xx | x86 | I & C | I & C | I only |
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* I = intrinsics; C = code generation
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*
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* Code can use the following constructs to determine compiler support & status:
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* - #ifdef __XXX__ (e.g: #ifdef __AVX__ or #ifdef __ARM_NEON__)
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* If this test passes, then the compiler is already generating code for that
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* given sub-architecture. The intrinsics for that sub-architecture are
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* #included and can be used without restriction or runtime check.
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*
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* - #if QT_COMPILER_SUPPORTS(XXX)
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* If this test passes, then the compiler is able to generate code for that
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* given sub-architecture in another translation unit, given the right set of
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* flags. Use of the intrinsics is not guaranteed. This is useful with
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* runtime detection (see below).
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*
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* - #if QT_COMPILER_SUPPORTS_HERE(XXX)
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* If this test passes, then the compiler is able to generate code for that
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* given sub-architecture in this translation unit, even if it is not doing
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* that now (it might be). Individual functions may be tagged with
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* QT_FUNCTION_TARGET(XXX) to cause the compiler to generate code for that
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* sub-arch. Only inside such functions is the use of the intrisics
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* guaranteed to work. This is useful with runtime detection (see below).
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*
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* Runtime detection of a CPU sub-architecture can be done with the
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* qCpuHasFeature(XXX) function. There are two strategies for generating
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* optimized code like that:
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*
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* 1) place the optimized code in a different translation unit (C or assembly
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* sources) and pass the correct flags to the compiler to enable support. Those
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* sources must not include qglobal.h, which means they cannot include this
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* file either. The dispatcher function would look like this:
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*
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* void foo()
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* {
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* #if QT_COMPILER_SUPPORTS(XXX)
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* if (qCpuHasFeature(XXX)) {
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* foo_optimized_xxx();
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* return;
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* }
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* #endif
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* foo_plain();
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* }
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*
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* 2) place the optimized code in a function tagged with QT_FUNCTION_TARGET and
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* surrounded by #if QT_COMPILER_SUPPORTS_HERE(XXX). That code can freely use
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* other Qt code. The dispatcher function would look like this:
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*
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* void foo()
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* {
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* #if QT_COMPILER_SUPPORTS_HERE(XXX)
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* if (qCpuHasFeature(XXX)) {
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* foo_optimized_xxx();
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* return;
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* }
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* #endif
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* foo_plain();
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* }
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*/
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#if defined(__MINGW64_VERSION_MAJOR) || defined(Q_CC_MSVC)
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#include <intrin.h>
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#endif
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#define QT_COMPILER_SUPPORTS(x) (QT_COMPILER_SUPPORTS_ ## x - 0)
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#if defined(Q_PROCESSOR_ARM) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS)
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# define QT_COMPILER_SUPPORTS_HERE(x) ((__ARM_FEATURE_ ## x) || (__ ## x ## __) || QT_COMPILER_SUPPORTS(x))
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# if defined(Q_CC_GNU)
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/* GCC requires attributes for a function */
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# define QT_FUNCTION_TARGET(x) __attribute__((__target__(QT_FUNCTION_TARGET_STRING_ ## x)))
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# else
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# define QT_FUNCTION_TARGET(x)
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# endif
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#elif defined(Q_PROCESSOR_MIPS)
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# define QT_COMPILER_SUPPORTS_HERE(x) (__ ## x ## __)
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# define QT_FUNCTION_TARGET(x)
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# if !defined(__MIPS_DSP__) && defined(__mips_dsp) && defined(Q_PROCESSOR_MIPS_32)
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# define __MIPS_DSP__
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# endif
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# if !defined(__MIPS_DSPR2__) && defined(__mips_dspr2) && defined(Q_PROCESSOR_MIPS_32)
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# define __MIPS_DSPR2__
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# endif
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#elif defined(Q_PROCESSOR_X86) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS)
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# if defined(Q_CC_CLANG) && defined(Q_CC_MSVC)
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# define QT_COMPILER_SUPPORTS_HERE(x) (__ ## x ## __)
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# else
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# define QT_COMPILER_SUPPORTS_HERE(x) ((__ ## x ## __) || QT_COMPILER_SUPPORTS(x))
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# endif
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# if defined(Q_CC_GNU) && !defined(Q_CC_INTEL)
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/* GCC requires attributes for a function */
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# define QT_FUNCTION_TARGET(x) __attribute__((__target__(QT_FUNCTION_TARGET_STRING_ ## x)))
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# else
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# define QT_FUNCTION_TARGET(x)
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# endif
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#elif defined(Q_PROCESSOR_ARM)
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# define QT_COMPILER_SUPPORTS_HERE(x) ((__ARM_FEATURE_ ## x) || (__ ## x ## __))
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# define QT_FUNCTION_TARGET(x)
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#else
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# define QT_COMPILER_SUPPORTS_HERE(x) (__ ## x ## __)
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# define QT_FUNCTION_TARGET(x)
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#endif
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#ifdef Q_PROCESSOR_X86
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/* -- x86 intrinsic support -- */
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# if defined(Q_CC_MSVC) && (defined(_M_X64) || _M_IX86_FP >= 2)
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// MSVC doesn't define __SSE2__, so do it ourselves
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# define __SSE__ 1
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# endif
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# if defined(Q_CC_GNU) && !defined(Q_CC_INTEL) && !defined(Q_OS_WASM)
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// GCC 4.4 and Clang 2.8 added a few more intrinsics there
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# include <x86intrin.h>
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# endif
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#ifdef Q_OS_WASM
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# include <immintrin.h>
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# endif
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# if defined(__SSE4_2__) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS) && (defined(Q_CC_INTEL) || defined(Q_CC_MSVC))
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// POPCNT instructions:
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// All processors that support SSE4.2 support POPCNT
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// (but neither MSVC nor the Intel compiler define this macro)
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# define __POPCNT__ 1
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# endif
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// AVX intrinsics
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# if defined(__AVX__) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS) && (defined(Q_CC_INTEL) || defined(Q_CC_MSVC))
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// PCLMULQDQ instructions:
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// All processors that support AVX support PCLMULQDQ
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// (but neither MSVC nor the Intel compiler define this macro)
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# define __PCLMUL__ 1
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# endif
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# if defined(__AVX2__) && defined(QT_COMPILER_SUPPORTS_SIMD_ALWAYS) && (defined(Q_CC_INTEL) || defined(Q_CC_MSVC))
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// F16C instructions:
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// All processors that support AVX2 support F16C:
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// (but neither MSVC nor the Intel compiler define this macro)
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# define __F16C__ 1
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# endif
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# if defined(__BMI__) && !defined(__BMI2__) && defined(Q_CC_INTEL)
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// BMI2 instructions:
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// All processors that support BMI support BMI2 (and AVX2)
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// (but neither MSVC nor the Intel compiler define this macro)
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# define __BMI2__ 1
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# endif
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# include "qsimd_x86_p.h"
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// Haswell sub-architecture
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//
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// The Intel Core 4th generation was codenamed "Haswell" and introduced AVX2,
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// BMI1, BMI2, FMA, LZCNT, MOVBE, which makes it a good divider for a
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// sub-target for us. The first AMD processor with AVX2 support (Zen) has the
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// same features.
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//
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// macOS's fat binaries support the "x86_64h" sub-architecture and the GNU libc
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// ELF loader also supports a "haswell/" subdir (e.g., /usr/lib/haswell).
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# define QT_FUNCTION_TARGET_STRING_ARCH_HASWELL "arch=haswell"
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# if defined(__AVX2__) && defined(__BMI__) && defined(__BMI2__) && defined(__F16C__) && \
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defined(__FMA__) && defined(__LZCNT__) && defined(__RDRND__)
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# define __haswell__ 1
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# endif
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// This constant does not include all CPU features found in a Haswell, only
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// those that we'd have optimized code for.
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// Note: must use Q_CONSTEXPR here, as this file may be compiled in C mode.
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QT_BEGIN_NAMESPACE
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static const quint64 CpuFeatureArchHaswell = 0
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| CpuFeatureSSE2
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| CpuFeatureSSE3
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| CpuFeatureSSSE3
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| CpuFeatureSSE4_1
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| CpuFeatureSSE4_2
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| CpuFeatureFMA
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| CpuFeaturePOPCNT
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| CpuFeatureAVX
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| CpuFeatureF16C
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| CpuFeatureAVX2
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| CpuFeatureBMI
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| CpuFeatureBMI2;
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QT_END_NAMESPACE
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#endif /* Q_PROCESSOR_X86 */
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// NEON intrinsics
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// note: as of GCC 4.9, does not support function targets for ARM
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#if defined(__ARM_NEON) || defined(__ARM_NEON__)
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#if defined(Q_CC_CLANG)
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#define QT_FUNCTION_TARGET_STRING_NEON "neon"
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#else
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#define QT_FUNCTION_TARGET_STRING_NEON "+neon" // unused: gcc doesn't support function targets on non-aarch64, and on Aarch64 NEON is always available.
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#endif
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#ifndef __ARM_NEON__
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// __ARM_NEON__ is not defined on AArch64, but we need it in our NEON detection.
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#define __ARM_NEON__
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#endif
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#ifndef Q_PROCESSOR_ARM_64 // vaddv is only available on Aarch64
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inline uint16_t vaddvq_u16(uint16x8_t v8)
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{
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const uint64x2_t v2 = vpaddlq_u32(vpaddlq_u16(v8));
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const uint64x1_t v1 = vadd_u64(vget_low_u64(v2), vget_high_u64(v2));
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return vget_lane_u16(vreinterpret_u16_u64(v1), 0);
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}
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inline uint8_t vaddv_u8(uint8x8_t v8)
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{
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const uint64x1_t v1 = vpaddl_u32(vpaddl_u16(vpaddl_u8(v8)));
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return vget_lane_u8(vreinterpret_u8_u64(v1), 0);
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}
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#endif
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#endif
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#if defined(Q_PROCESSOR_ARM) && defined(__ARM_FEATURE_CRC32)
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# include <arm_acle.h>
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#endif
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#if defined(Q_PROCESSOR_ARM_64)
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#if defined(Q_CC_CLANG)
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#define QT_FUNCTION_TARGET_STRING_AES "crypto"
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#define QT_FUNCTION_TARGET_STRING_CRC32 "crc"
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#elif defined(Q_CC_GNU)
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#define QT_FUNCTION_TARGET_STRING_AES "+crypto"
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#define QT_FUNCTION_TARGET_STRING_CRC32 "+crc"
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#endif
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#elif defined(Q_PROCESSOR_ARM_32)
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#if defined(Q_CC_CLANG)
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#define QT_FUNCTION_TARGET_STRING_AES "armv8-a,crypto"
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#define QT_FUNCTION_TARGET_STRING_CRC32 "armv8-a,crc"
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#elif defined(Q_CC_GNU)
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#define QT_FUNCTION_TARGET_STRING_AES "arch=armv8-a+crypto"
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#define QT_FUNCTION_TARGET_STRING_CRC32 "arch=armv8-a+crc"
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#endif
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#endif
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#ifdef __cplusplus
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#include <qatomic.h>
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QT_BEGIN_NAMESPACE
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#ifndef Q_PROCESSOR_X86
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enum CPUFeatures {
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#if defined(Q_PROCESSOR_ARM)
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CpuFeatureNEON = 2,
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CpuFeatureARM_NEON = CpuFeatureNEON,
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CpuFeatureCRC32 = 4,
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CpuFeatureAES = 8,
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CpuFeatureARM_CRYPTO = CpuFeatureAES,
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#elif defined(Q_PROCESSOR_MIPS)
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CpuFeatureDSP = 2,
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CpuFeatureDSPR2 = 4,
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#endif
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// used only to indicate that the CPU detection was initialised
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QSimdInitialized = 1
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};
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static const quint64 qCompilerCpuFeatures = 0
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#if defined __ARM_NEON__
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| CpuFeatureNEON
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#endif
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#if defined __ARM_FEATURE_CRC32
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| CpuFeatureCRC32
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#endif
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#if defined __ARM_FEATURE_CRYPTO
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| CpuFeatureAES
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#endif
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#if defined __mips_dsp
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| CpuFeatureDSP
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#endif
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#if defined __mips_dspr2
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| CpuFeatureDSPR2
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#endif
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;
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#endif
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#ifdef Q_ATOMIC_INT64_IS_SUPPORTED
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extern Q_CORE_EXPORT QBasicAtomicInteger<quint64> qt_cpu_features[1];
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#else
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extern Q_CORE_EXPORT QBasicAtomicInteger<unsigned> qt_cpu_features[2];
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#endif
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Q_CORE_EXPORT quint64 qDetectCpuFeatures();
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#if defined(Q_PROCESSOR_X86) && QT_COMPILER_SUPPORTS_HERE(RDRND) && !defined(QT_BOOTSTRAPPED)
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Q_CORE_EXPORT qsizetype qRandomCpu(void *, qsizetype) noexcept;
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#else
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static inline qsizetype qRandomCpu(void *, qsizetype) noexcept
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{
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return 0;
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}
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#endif
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static inline quint64 qCpuFeatures()
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{
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quint64 features = qt_cpu_features[0].loadRelaxed();
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#ifndef Q_ATOMIC_INT64_IS_SUPPORTED
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features |= quint64(qt_cpu_features[1].loadRelaxed()) << 32;
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#endif
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if (Q_UNLIKELY(features == 0)) {
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features = qDetectCpuFeatures();
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Q_ASSUME(features != 0);
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}
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return features;
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}
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#define qCpuHasFeature(feature) (((qCompilerCpuFeatures & CpuFeature ## feature) == CpuFeature ## feature) \
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|| ((qCpuFeatures() & CpuFeature ## feature) == CpuFeature ## feature))
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inline bool qHasHwrng()
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{
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#if defined(Q_PROCESSOR_X86) && QT_COMPILER_SUPPORTS_HERE(RDRND)
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return qCpuHasFeature(RDRND);
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#else
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return false;
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#endif
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}
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#define ALIGNMENT_PROLOGUE_16BYTES(ptr, i, length) \
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for (; i < static_cast<int>(qMin(static_cast<quintptr>(length), ((4 - ((reinterpret_cast<quintptr>(ptr) >> 2) & 0x3)) & 0x3))); ++i)
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#define ALIGNMENT_PROLOGUE_32BYTES(ptr, i, length) \
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for (; i < static_cast<int>(qMin(static_cast<quintptr>(length), ((8 - ((reinterpret_cast<quintptr>(ptr) >> 2) & 0x7)) & 0x7))); ++i)
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QT_END_NAMESPACE
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#endif // __cplusplus
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#define SIMD_EPILOGUE(i, length, max) \
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for (int _i = 0; _i < max && i < length; ++i, ++_i)
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#endif // QSIMD_P_H
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