9 Commits

Author SHA1 Message Date
Allan Sandfeld Jensen
fe6dc9dc85 Add runtime ARM64 AES check
Adds runtime CPU detection for Windows and macOS, and switches feature
detection of AES to runtime like for x86,

So far only on ARM64, since gcc doesn't do function versioning on ARM32,
but clang can, so it could be added later.

Change-Id: Ibe5d60f48cdae3e366a8ecd6263534ba2b09b131
Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@qt.io>
Reviewed-by: Alexandru Croitor <alexandru.croitor@qt.io>
2021-05-20 18:31:05 +00:00
Allan Sandfeld Jensen
3b8031059a Fix missing CPU feature feedback
Add empty string first like we have for x86.
This fixes offset checks, and reported missing features.

Pick-to: 6.1
Change-Id: I09f6be05641d5ed9ae5d91fa72f678fef60bdbe7
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2021-04-21 22:57:04 +02:00
Allan Sandfeld Jensen
ed82e1304d Cleanup qsimd ARM code
Switch to using getauxval.

Change-Id: I1a55cf24e3cacbbca1f57ad6f74a80df80fe60cf
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2021-04-21 15:01:13 +02:00
Allan Sandfeld Jensen
8179d7edf6 Add runtime aes/crypto check for ARM
Yocto apparantly enables it hard at compile time.

Change-Id: I1d4c7402eacc714859c61f469ebed85682d48b51
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2021-04-21 15:01:13 +02:00
Allan Sandfeld Jensen
ccd17fbc57 Fix ARM and MIPS runtime CPU feature flags
The set values didn't match tested values, as the enum were already
on flag form.

Pick-to: 6.1 6.0 5.15
Change-Id: I9e8b0d419682122e8d40cd47bd68d840386c2066
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2021-04-20 00:26:12 +02:00
Allan Sandfeld Jensen
ff776a3059 Whitespace cleanup in corelib/global
Change-Id: I087d7d949cfd43e48e8a008621a4eeaa9d104ceb
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
2020-10-21 21:15:17 +02:00
Thiago Macieira
034427a45a Deal with macOS not enabling AVX512 state in XCR0
All Mac Pros launched since 2019 have AVX512 support (CLX processor) but
the Darwin kernel does not enable the state bits in the XCR0 register
for all processes by default. Instead, it traps the #UD exception and
decodes the instruction to find out if it was an AVX512 instruction. If
so, it adds memory to the thread's context switch space. See [1].

Good solution, but forces us to have OS-specific code to determine if
the OS really supports AVX512. No other OS appears to require this. For
future features (namely, Intel Advanced Matrix Extensions), there's an
official way of implementing this, via the eXtended Feature Disable
register.

Qt has no AVX512 code yet, so this is just being future-proof. Apple has
yet to announce when or if their Mac Pros will switch from Intel Xeon to
ARM.

[1] https://github.com/apple/darwin-xnu/blob/xnu-4903.221.2/osfmk/i386/fpu.c#L174

Change-Id: Ieffc3453b88c4517a1dbfffd162175ead343e622
Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@qt.io>
2020-07-22 10:46:09 -07:00
Thiago Macieira
0de4f0dcc3 Fix build of rdrand & rdseed with ICC on Linux
qsimd.cpp(636): error: argument of type "qregisteruint={quint64={unsigned long long}} *" is incompatible with parameter of type "unsigned long *"

Pick-To: 5.15
Change-Id: I99ab0f318b1c43b89888fffd160c4785c98adc4d
Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2020-05-06 01:58:50 -07:00
Lars Knoll
f2f32b88b8 Move qsimd* from corelib/tools to corelib/global
It's not used in tools at all and fits a lot better in global.

Also fix the qsimd_x86* files to have a proper copyright
header.

Change-Id: Id3d8e7cfcd7769a1ca9f3d8cf6d357a31a99ba40
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
2020-03-26 09:15:32 +01:00