diff --git a/src/corelib/global/archdetect.cpp b/src/corelib/global/archdetect.cpp
index 66a5e074f62..1d00b7f5a52 100644
--- a/src/corelib/global/archdetect.cpp
+++ b/src/corelib/global/archdetect.cpp
@@ -67,6 +67,10 @@
 #  define ARCH_PROCESSOR "power"
 #elif defined(Q_PROCESSOR_POWER_64)
 #  define ARCH_PROCESSOR "power64"
+#elif defined(Q_PROCESSOR_RISCV_32)
+#  define ARCH_PROCESSOR "riscv32"
+#elif defined(Q_PROCESSOR_RISCV_64)
+#  define ARCH_PROCESSOR "riscv64"
 #elif defined(Q_PROCESSOR_S390_X)
 #  define ARCH_PROCESSOR "s390x"
 #elif defined(Q_PROCESSOR_S390)
diff --git a/src/corelib/global/qglobal.cpp b/src/corelib/global/qglobal.cpp
index d95064af278..16d8d8b8ac8 100644
--- a/src/corelib/global/qglobal.cpp
+++ b/src/corelib/global/qglobal.cpp
@@ -1883,6 +1883,42 @@ bool qSharedBuild() noexcept
     \sa QSysInfo::buildCpuArchitecture()
 */
 
+/*!
+    \macro Q_PROCESSOR_RISCV
+    \relates <QtGlobal>
+    \since 5.13
+
+    Defined if the application is compiled for RISC-V processors. Qt currently
+    supports two RISC-V variants: \l Q_PROCESSOR_RISCV_32 and \l
+    Q_PROCESSOR_RISCV_64.
+
+    \sa QSysInfo::buildCpuArchitecture()
+*/
+
+/*!
+    \macro Q_PROCESSOR_RISCV_32
+    \relates <QtGlobal>
+    \since 5.13
+
+    Defined if the application is compiled for 32-bit RISC-V processors. The \l
+    Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_32 is
+    defined.
+
+    \sa QSysInfo::buildCpuArchitecture()
+*/
+
+/*!
+    \macro Q_PROCESSOR_RISCV_64
+    \relates <QtGlobal>
+    \since 5.13
+
+    Defined if the application is compiled for 64-bit RISC-V processors. The \l
+    Q_PROCESSOR_RISCV macro is also defined when Q_PROCESSOR_RISCV_64 is
+    defined.
+
+    \sa QSysInfo::buildCpuArchitecture()
+*/
+
 /*!
     \macro Q_PROCESSOR_S390
     \relates <QtGlobal>
diff --git a/src/corelib/global/qprocessordetection.h b/src/corelib/global/qprocessordetection.h
index 1f327c352ec..8d657208503 100644
--- a/src/corelib/global/qprocessordetection.h
+++ b/src/corelib/global/qprocessordetection.h
@@ -281,6 +281,20 @@
 #  endif
 // Q_BYTE_ORDER not defined, use endianness auto-detection
 
+/*
+    RISC-V family, known variants: 32- and 64-bit
+
+    RISC-V is little-endian.
+*/
+#elif defined(__riscv)
+#  define Q_PROCESSOR_RISCV
+#  if __riscv_xlen == 64
+#    define Q_PROCESSOR_RISCV_64
+#  else
+#    define Q_PROCESSOR_RISCV_32
+#  endif
+#  define Q_BYTE_ORDER Q_LITTLE_ENDIAN
+
 /*
     S390 family, known variant: S390X (64-bit)