Add LSX and LASX configure detection
Adds loongarch simd extension(LSX LASX) configure test and -feature-lsx and -feature-lasx configure options. Add detection of LSX and LASX at run-time in qsimd.cpp. Change-Id: I63eab2f4f45c306b672a89b376e0cbc01da0df83 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io> Reviewed-by: Volker Hilsheimer <volker.hilsheimer@qt.io>
This commit is contained in:
Chen Zhanwang
Volker Hilsheimer
parent
6d49bd766f
commit
73ce5a940a
@ -68,6 +68,8 @@ if(GCC OR CLANG OR QCC)
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endif()
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set(QT_CFLAGS_ARM_SVE "${__prefix}-march=armv8-a+sve")
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set(QT_CFLAGS_ARM_CRYPTO "${__prefix}-march=armv8-a+crypto")
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set(QT_CFLAGS_LSX "${__prefix}-mlsx")
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set(QT_CFLAGS_LASX "${__prefix}-mlasx")
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set(QT_CFLAGS_MIPS_DSP "${__prefix}-mdsp")
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set(QT_CFLAGS_MIPS_DSPR2 "${__prefix}-mdspr2")
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unset(__prefix)
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@ -1308,6 +1308,31 @@ function(qt_config_compile_test_armintrin extension label)
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set(TEST_subarch_${extension} "${TEST_ARMINTRIN_${extension}}" CACHE INTERNAL "${label}")
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endfunction()
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function(qt_config_compile_test_loongarchsimd extension label)
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if (DEFINED TEST_LOONGARCHSIMD_${extension})
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return()
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endif()
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set(flags "-DSIMD:string=${extension}")
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qt_get_platform_try_compile_vars(platform_try_compile_vars)
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list(APPEND flags ${platform_try_compile_vars})
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message(STATUS "Performing Test ${label} intrinsics")
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try_compile("TEST_LOONGARCHSIMD_${extension}"
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"${CMAKE_CURRENT_BINARY_DIR}/config.tests/loongarch_simd_${extension}"
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"${CMAKE_CURRENT_SOURCE_DIR}/config.tests/loongarch_simd"
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loongarch_simd
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CMAKE_FLAGS ${flags})
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if(${TEST_LOONGARCHSIMD_${extension}})
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set(status_label "Success")
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else()
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set(status_label "Failed")
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endif()
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message(STATUS "Performing Test ${label} intrinsics - ${status_label}")
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set(TEST_subarch_${extension} "${TEST_LOONGARCHSIMD_${extension}}" CACHE INTERNAL "${label}")
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endfunction()
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function(qt_config_compile_test_machine_tuple label)
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if(DEFINED TEST_MACHINE_TUPLE OR NOT (LINUX OR HURD) OR ANDROID)
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return()
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@ -245,6 +245,7 @@ defstub(qt_config_compile_test)
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defstub(qt_config_compile_test_armintrin)
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defstub(qt_config_compile_test_machine_tuple)
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defstub(qt_config_compile_test_x86simd)
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defstub(qt_config_compile_test_loongarchsimd)
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defstub(qt_config_compiler_supports_flag_test)
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defstub(qt_config_linker_supports_flag_test)
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defstub(qt_configure_add_report_entry)
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26
config.tests/loongarch_simd/CMakeLists.txt
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26
config.tests/loongarch_simd/CMakeLists.txt
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@ -0,0 +1,26 @@
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# Copyright (C) 2022 The Qt Company Ltd.
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# SPDX-License-Identifier: BSD-3-Clause
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cmake_minimum_required(VERSION 3.16)
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project(loongarch_simd LANGUAGES CXX)
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include(../../cmake/QtPlatformSupport.cmake)
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include(../../cmake/QtCompilerOptimization.cmake)
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# FIXME: Make the this project handle a list of SIMD entries.
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# FIXME: Make this project handle appending of the cflags (similar to the qmake project).
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# This is needed for the loongarchsimd configure test (
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# aka we test to see if setting no SIMD (-mlsx) cflags at all, will result in their implicit
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# addition by the compiler).
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string(TOUPPER "${SIMD}" upper_simd)
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if(NOT DEFINED "QT_CFLAGS_${upper_simd}")
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# Don't use CMake error() because a configure error also fails the try_compile() call.
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# Instead use a compile flag that doesn't exist to force a compiler error.
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set(QT_CFLAGS_${upper_simd} "--qt-cflags-not-found")
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endif()
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add_executable("SimdTest${SIMD}")
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target_sources("SimdTest${SIMD}" PRIVATE main.cpp)
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target_compile_options("SimdTest${SIMD}" PRIVATE ${QT_CFLAGS_${upper_simd}})
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target_compile_definitions("SimdTest${SIMD}" PRIVATE QT_COMPILER_SUPPORTS_${upper_simd})
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29
config.tests/loongarch_simd/main.cpp
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29
config.tests/loongarch_simd/main.cpp
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@ -0,0 +1,29 @@
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// Copyright (C) 2017 Intel Corporation.
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// SPDX-License-Identifier: BSD-3-Clause
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#define T(x) (QT_COMPILER_SUPPORTS_ ## x)
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#if T(LSX)
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#include <lsxintrin.h>
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void test_lsx()
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{
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__m128i a = __lsx_vldi(0);
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(void) __lsx_vshuf_h(__lsx_vldi(0), a, a);
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}
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#endif
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#if T(LASX)
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#include <lsxintrin.h>
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#include <lasxintrin.h>
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void test_lasx()
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{
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__m256i a = __lasx_xvldi(0);
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__m256i b = __lasx_xvadd_b(a, a);
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(void) __lasx_xvadd_b(a, b);
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}
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#endif
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int main()
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{
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return 0;
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}
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@ -376,6 +376,12 @@ qt_config_compile_test_armintrin(crypto "CRYPTO")
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# arm: sve
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qt_config_compile_test_armintrin(sve "SVE")
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# loongarch: lsx
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qt_config_compile_test_loongarchsimd(lsx "LSX")
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# loongarch: lasx
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qt_config_compile_test_loongarchsimd(lasx "LASX")
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# localtime_r
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qt_config_compile_test(localtime_r
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LABEL "localtime_r()"
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@ -901,6 +907,18 @@ qt_feature("shani" PRIVATE
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)
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qt_feature_definition("shani" "QT_COMPILER_SUPPORTS_SHA" VALUE "1")
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qt_feature_config("shani" QMAKE_PRIVATE_CONFIG)
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qt_feature("lsx" PRIVATE
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LABEL "LSX"
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CONDITION ( TEST_architecture_arch STREQUAL loongarch64 ) AND TEST_subarch_lsx
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)
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qt_feature_definition("lsx" "QT_COMPILER_SUPPORTS_LSX" VALUE "1")
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qt_feature_config("lsx" QMAKE_PRIVATE_CONFIG)
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qt_feature("lasx" PRIVATE
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LABEL "LASX"
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CONDITION ( TEST_architecture_arch STREQUAL loongarch64 ) AND TEST_subarch_lasx
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)
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qt_feature_definition("lasx" "QT_COMPILER_SUPPORTS_LASX" VALUE "1")
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qt_feature_config("lasx" QMAKE_PRIVATE_CONFIG)
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qt_feature("mips_dsp" PRIVATE
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LABEL "DSP"
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CONDITION ( TEST_architecture_arch STREQUAL mips ) AND TEST_arch_${TEST_architecture_arch}_subarch_dsp
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@ -1301,6 +1319,12 @@ qt_configure_add_summary_entry(
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MESSAGE "ARM Extensions"
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CONDITION ( TEST_architecture_arch STREQUAL arm ) OR ( TEST_architecture_arch STREQUAL arm64 )
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)
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qt_configure_add_summary_entry(
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TYPE "featureList"
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ARGS "lsx lasx"
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MESSAGE "LOONGARCH Extensions"
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CONDITION ( TEST_architecture_arch STREQUAL loongarch64 )
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)
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qt_configure_add_summary_entry(
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ARGS "mips_dsp"
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CONDITION ( TEST_architecture_arch STREQUAL mips )
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@ -119,6 +119,8 @@ QMAKE_CFLAGS_VAES += -mvaes
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QMAKE_CFLAGS_NEON += -mfpu=neon
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QMAKE_CFLAGS_MIPS_DSP += -mdsp
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QMAKE_CFLAGS_MIPS_DSPR2 += -mdspr2
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QMAKE_CFLAGS_LSX += -mlsx
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QMAKE_CFLAGS_LASX += -mlasx
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# -march=haswell is supported as of GCC 4.9 and Clang 3.6
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QMAKE_CFLAGS_ARCH_HASWELL = -march=core-avx2
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@ -146,6 +146,8 @@ addSimdCompiler(rdseed)
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addSimdCompiler(neon)
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addSimdCompiler(mips_dsp)
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addSimdCompiler(mips_dspr2)
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addSimdCompiler(lsx)
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addSimdCompiler(lasx)
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# Haswell sub-architecture
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defineTest(addSimdArch) {
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@ -33,7 +33,7 @@
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# endif
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#elif defined(Q_OS_LINUX) && defined(Q_PROCESSOR_MIPS_32)
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# include "private/qcore_unix_p.h"
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#elif QT_CONFIG(getauxval) && defined(Q_PROCESSOR_ARM)
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#elif QT_CONFIG(getauxval) && (defined(Q_PROCESSOR_ARM) || defined(Q_PROCESSOR_LOONGARCH))
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# include <sys/auxv.h>
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// the kernel header definitions for HWCAP_*
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@ -95,6 +95,19 @@ static const char features_string[] =
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" dsp\0"
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" dspr2\0";
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static const int features_indices[] = {
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0, 1, 6
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};
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#elif defined(Q_PROCESSOR_LOONGARCH)
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/* Data:
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lsx
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lasx
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*/
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static const char features_string[] =
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"\0"
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" lsx\0"
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" lasx\0";
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static const int features_indices[] = {
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0, 1, 6
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};
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@ -192,6 +205,40 @@ static inline quint64 detectProcessorFeatures()
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return features;
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}
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#elif defined(Q_PROCESSOR_LOONGARCH)
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static inline quint64 detectProcessorFeatures()
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{
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quint64 features = 0;
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# if QT_CONFIG(getauxval)
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quint64 hwcap = getauxval(AT_HWCAP);
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if (hwcap & HWCAP_LOONGARCH_LSX)
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features |= CpuFeatureLSX;
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if (hwcap & HWCAP_LOONGARCH_LASX)
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features |= CpuFeatureLASX;
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# else
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enum LoongArchFeatures {
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LOONGARCH_CFG2 = 0x2,
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LOONGARCH_CFG2_LSX = (1 << 6),
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LOONGARCH_CFG2_LASX = (1 << 7)
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};
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quint64 reg = 0;
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__asm__ volatile(
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"cpucfg %0, %1 \n\t"
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: "+&r"(reg)
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: "r"(LOONGARCH_CFG2)
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);
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if (reg & LOONGARCH_CFG2_LSX)
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features |= CpuFeatureLSX;
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if (reg & LOONGARCH_CFG2_LASX)
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features |= CpuFeatureLASX;
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# endif
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return features;
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}
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#elif defined(Q_PROCESSOR_X86)
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#ifdef Q_PROCESSOR_X86_32
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@ -21,6 +21,8 @@
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* sse4_1 | x86
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* sse4_2 | x86
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* avx | x86
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* lsx | loongarch
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* lasx | loongarch
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*
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* Code can use the following constructs to determine compiler support & status:
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* - #if QT_COMPILER_USES(XXX) (e.g: #if QT_COMPILER_USES(neon) or QT_COMPILER_USES(sse4_1)
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@ -53,6 +55,20 @@
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# define QT_COMPILER_USES_mips_dspr2 -1
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#endif
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#if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_sx)
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# include <lsxintrin.h>
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# define QT_COMPILER_USES_lsx 1
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#else
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# define QT_COMPILER_USES_lsx -1
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#endif
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#if defined(Q_PROCESSOR_LOONGARCH) && defined(__loongarch_asx)
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# include <lasxintrin.h>
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# define QT_COMPILER_USES_lasx 1
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#else
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# define QT_COMPILER_USES_lasx -1
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#endif
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#if defined(Q_PROCESSOR_X86) && defined(Q_CC_MSVC)
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// MSVC doesn't define __SSE2__, so do it ourselves
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# if (defined(_M_X64) || _M_IX86_FP >= 2) && defined(QT_COMPILER_SUPPORTS_SSE2)
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@ -120,6 +120,9 @@ QT_WARNING_DISABLE_INTEL(103)
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# if !defined(__MIPS_DSPR2__) && defined(__mips_dspr2) && defined(Q_PROCESSOR_MIPS_32)
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# define __MIPS_DSPR2__
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# endif
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#elif defined(Q_PROCESSOR_LOONGARCH)
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# define QT_COMPILER_SUPPORTS_HERE(x) QT_COMPILER_SUPPORTS(x)
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# define QT_FUNCTION_TARGET(x)
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#elif defined(Q_PROCESSOR_X86)
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# if defined(Q_CC_CLANG) && defined(Q_CC_MSVC)
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# define QT_COMPILER_SUPPORTS_HERE(x) (__ ## x ## __)
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@ -383,6 +386,9 @@ enum CPUFeatures {
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#elif defined(Q_PROCESSOR_MIPS)
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CpuFeatureDSP = 2,
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CpuFeatureDSPR2 = 4,
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#elif defined(Q_PROCESSOR_LOONGARCH)
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CpuFeatureLSX = 2,
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CpuFeatureLASX = 4,
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#endif
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};
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@ -411,6 +417,12 @@ static const uint64_t qCompilerCpuFeatures = 0
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#endif
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#if defined __mips_dspr2
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| CpuFeatureDSPR2
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#endif
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#if defined __loongarch_sx
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| CpuFeatureLSX
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#endif
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#if defined __loongarch_asx
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| CpuFeatureLASX
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#endif
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;
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#endif
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