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Update listing of when SSSE3 and SSE4.1 first became available

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SSSE3 was first available on the original Intel Core 2 processors, so
add the "Merom" codename. SSE4.1 was available on the 45 nm shrink of
those processors, codename "Penryn", not on the next architecture.

Change-Id: I5fd92db62aa409b7f4e46f9b24d960519177f811
Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
This commit is contained in:
Thiago Macieira 2012-06-12 14:44:24 +02:00 committed by Qt by Nokia
parent b4525b3407
commit 53546ce0b6
1 changed files with 2 additions and 2 deletions
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4
config.tests/arch/arch.cpp
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@ -182,7 +182,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
" sse3" " sse3"
#endif #endif
#ifdef __SSSE3__ #ifdef __SSSE3__
// Supplemental SSE3, Intel Core 2, AMD "Bulldozer" // Supplemental SSE3, Intel Core 2 ("Merom"), AMD "Bulldozer"
" ssse3" " ssse3"
#endif #endif
#ifdef __SSE4A__ #ifdef __SSE4A__
@ -190,7 +190,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
" sse4a" " sse4a"
#endif #endif
#ifdef __SSE4_1__ #ifdef __SSE4_1__
// SSE 4.1, Intel Core-i7 ("Nehalem"), AMD "Bulldozer" // SSE 4.1, Intel Core2 45nm shrink ("Penryn"), AMD "Bulldozer"
" sse4.1" " sse4.1"
#endif #endif
#ifdef __SSE4_2__ #ifdef __SSE4_2__