Add ARM SVE detection
Limited to ARM64 and little-endian to keep our code simple. Change-Id: Ie65f71a31ca98d6929561d4b2ee1e9332b3a82d8 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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@ -66,6 +66,7 @@ if(GCC OR CLANG OR QCC)
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if(NOT UIKIT AND NOT QT_64BIT)
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set(QT_CFLAGS_NEON "${__prefix}-mfpu=neon")
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endif()
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set(QT_CFLAGS_ARM_SVE "${__prefix}-march=armv8-a+sve")
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set(QT_CFLAGS_MIPS_DSP "${__prefix}-mdsp")
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set(QT_CFLAGS_MIPS_DSPR2 "${__prefix}-mdspr2")
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unset(__prefix)
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@ -251,6 +251,9 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
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#if defined(__ARM_FEATURE_CRYPTO) || (defined(_M_ARM64) && __ARM_ARCH >= 800)
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" crypto"
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#endif
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#ifdef __ARM_FEATURE_SVE
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" sve"
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#endif
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// -- SPARC --
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#ifdef __VIS__
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@ -929,6 +929,13 @@ qt_feature_definition("arm_crypto" "QT_COMPILER_SUPPORTS_CRYPTO" VALUE "1")
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qt_feature_definition("arm_crypto" "QT_COMPILER_SUPPORTS_AES" VALUE "1")
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qt_feature_config("arm_crypto" QMAKE_PRIVATE_CONFIG)
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qt_feature("arm_sve" PRIVATE
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LABEL "SVE"
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CONDITION ( TEST_architecture_arch STREQUAL arm64 ) AND TEST_arch_${TEST_architecture_arch}_subarch_sve
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)
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qt_feature_definition("arm_sve" "QT_COMPILER_SUPPORTS_SVE" VALUE "1")
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qt_feature_config("arm_sve" QMAKE_PRIVATE_CONFIG)
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qt_feature("wasm-simd128" PUBLIC
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LABEL "WebAssembly SIMD128"
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PURPOSE "Enables WebAssembly SIMD"
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@ -49,6 +49,7 @@
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// copied from <asm/hwcap.h> (Aarch64)
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#define HWCAP_AES (1 << 3)
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#define HWCAP_CRC32 (1 << 7)
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#define HWCAP_SVE (1 << 22)
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// copied from <linux/auxvec.h>
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#define AT_HWCAP 16 /* arch dependent hints at CPU capabilities */
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@ -75,13 +76,15 @@ uint arraysize(T (&)[N])
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neon
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crc32
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aes
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sve
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*/
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static const char features_string[] =
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"\0"
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" neon\0"
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" crc32\0"
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" aes\0";
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static const int features_indices[] = { 0, 1, 7, 14 };
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" aes\0"
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" sve\0";
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static const int features_indices[] = { 0, 1, 7, 14, 19 };
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#elif defined(Q_PROCESSOR_MIPS)
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/* Data:
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dsp
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@ -118,6 +121,8 @@ static inline quint64 detectProcessorFeatures()
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features |= CpuFeatureCRC32;
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if (auxvHwCap & HWCAP_AES)
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features |= CpuFeatureAES;
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if (auxvHwCap & HWCAP_SVE)
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features |= CpuFeatureSVE;
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# else
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// For ARM32:
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if (auxvHwCap & HWCAP_NEON)
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@ -155,6 +160,12 @@ static inline quint64 detectProcessorFeatures()
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#else
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if (sysctlbyname("hw.optional.arm.FEAT_AES", &feature, &len, nullptr, 0) == 0)
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features |= feature ? CpuFeatureAES : 0;
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#endif
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#if defined(__ARM_FEATURE_SVE)
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features |= CpuFeatureSVE;
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#else
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if (sysctlbyname("hw.optional.arm.FEAT_SVE", &feature, &len, nullptr, 0) == 0)
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features |= feature ? CpuFeatureSVE : 0;
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#endif
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return features;
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#elif defined(Q_OS_WIN) && defined(Q_PROCESSOR_ARM_64)
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@ -174,6 +185,9 @@ static inline quint64 detectProcessorFeatures()
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#if defined(__ARM_FEATURE_CRYPTO)
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features |= CpuFeatureAES;
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#endif
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#if defined(__ARM_FEATURE_SVE)
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features |= CpuFeatureSVE;
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#endif
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return features;
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}
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@ -347,12 +347,15 @@ inline uint32x4_t qvsetq_n_u32(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
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#if defined(Q_CC_CLANG)
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#define QT_FUNCTION_TARGET_STRING_AES "crypto"
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#define QT_FUNCTION_TARGET_STRING_CRC32 "crc"
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#define QT_FUNCTION_TARGET_STRING_SVE "sve"
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#elif defined(Q_CC_GNU)
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#define QT_FUNCTION_TARGET_STRING_AES "+crypto"
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#define QT_FUNCTION_TARGET_STRING_CRC32 "+crc"
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#define QT_FUNCTION_TARGET_STRING_SVE "+sve"
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#elif defined(Q_CC_MSVC)
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#define QT_FUNCTION_TARGET_STRING_AES
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#define QT_FUNCTION_TARGET_STRING_CRC32
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#define QT_FUNCTION_TARGET_STRING_SVE
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#endif
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#elif defined(Q_PROCESSOR_ARM_32)
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#if defined(Q_CC_CLANG)
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@ -372,6 +375,7 @@ enum CPUFeatures {
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CpuFeatureCRC32 = 4,
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CpuFeatureAES = 8,
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CpuFeatureARM_CRYPTO = CpuFeatureAES,
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CpuFeatureSVE = 16,
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#elif defined(Q_PROCESSOR_MIPS)
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CpuFeatureDSP = 2,
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CpuFeatureDSPR2 = 4,
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@ -395,6 +399,9 @@ static const uint64_t qCompilerCpuFeatures = 0
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| CpuFeatureAES
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#endif
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#endif // Q_OS_LINUX && Q_PROCESSOR_ARM64
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#if defined(__ARM_FEATURE_SVE) && defined(Q_PROCESSOR_ARM_64)
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| CpuFeatureSVE
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#endif
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#if defined __mips_dsp
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| CpuFeatureDSP
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#endif
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