Expand reporting of the Intel instruction set extensions
Detection for most of them is free because we're loading the entire registers anyway. The only exception is AVX512VBMI, which is in a new register we hadn't yet read from. I've also added the new GCC names so they can be used with QT_FUNCTION_TARGET. The only two exceptions are "movbe" and "popcnt", which are extremely restricted in use and we are not likely to have code dedicated to using them. Change-Id: Ib306f8f647014b399b87ffff13f1d8fd29e58be0 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
This commit is contained in:
Thiago Macieira
parent
6a8251a89b
commit
0829baf902
@ -205,21 +205,24 @@ static void cpuidFeatures01(uint &ecx, uint &edx)
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inline void __cpuidex(int info[4], int, __int64) { memset(info, 0, 4*sizeof(int));}
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#endif
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static void cpuidFeatures07_00(uint &ebx)
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static void cpuidFeatures07_00(uint &ebx, uint &ecx)
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{
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#if defined(Q_CC_GNU)
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qregisteruint rbx; // in case it's 64-bit
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qregisteruint rcx = 0;
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asm ("xchg " PICreg", %0\n"
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"cpuid\n"
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"xchg " PICreg", %0\n"
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: "=&r" (rbx)
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: "a" (7), "c" (0)
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: "=&r" (rbx), "+&c" (rcx)
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: "a" (7)
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: "%edx");
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ebx = rbx;
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ecx = rcx;
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#elif defined(Q_OS_WIN)
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int info[4];
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__cpuidex(info, 7, 0);
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ebx = info[1];
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ecx = info[2];
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#endif
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}
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@ -257,7 +260,12 @@ static quint64 detectProcessorFeatures()
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AVXState = XMM0_15 | YMM0_15Hi128,
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AVX512State = AVXState | OpMask | ZMM0_15Hi256 | ZMM16_31
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};
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static const quint64 AllAVX2 = (Q_UINT64_C(1) << CpuFeatureAVX2);
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static const quint64 AllAVX512 = (Q_UINT64_C(1) << CpuFeatureAVX512F) | (Q_UINT64_C(1) << CpuFeatureAVX512CD) |
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(Q_UINT64_C(1) << CpuFeatureAVX512ER) | (Q_UINT64_C(1) << CpuFeatureAVX512PF) |
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(Q_UINT64_C(1) << CpuFeatureAVX512BW) | (Q_UINT64_C(1) << CpuFeatureAVX512DQ) |
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(Q_UINT64_C(1) << CpuFeatureAVX512VL) |
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(Q_UINT64_C(1) << CpuFeatureAVX512IFMA) | (Q_UINT64_C(1) << CpuFeatureAVX512VBMI);
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static const quint64 AllAVX2 = (Q_UINT64_C(1) << CpuFeatureAVX2) | AllAVX512;
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static const quint64 AllAVX = (Q_UINT64_C(1) << CpuFeatureAVX) | AllAVX2;
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quint64 features = 0;
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@ -295,8 +303,9 @@ static quint64 detectProcessorFeatures()
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}
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uint cpuid0700EBX = 0;
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uint cpuid0700ECX = 0;
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if (cpuidLevel >= 7) {
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cpuidFeatures07_00(cpuid0700EBX);
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cpuidFeatures07_00(cpuid0700EBX, cpuid0700ECX);
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// the high 32-bits of features is cpuid0700EBX
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features |= quint64(cpuid0700EBX) << 32;
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@ -305,6 +314,15 @@ static quint64 detectProcessorFeatures()
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if ((xgetbvA & AVXState) != AVXState) {
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// support for YMM registers is disabled, disable all AVX
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features &= ~AllAVX;
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} else if ((xgetbvA & AVX512State) != AVX512State) {
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// support for ZMM registers or mask registers is disabled, disable all AVX512
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features &= ~AllAVX512;
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} else {
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// this feature is out of order
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if (cpuid0700ECX & (1u << 1))
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features |= Q_UINT64_C(1) << CpuFeatureAVX512VBMI;
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else
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features &= ~(Q_UINT64_C(1) << CpuFeatureAVX512VBMI);
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}
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return features;
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@ -484,7 +502,7 @@ static const int features_indices[] = {
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/* Data:
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sse3
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sse2
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avx512vbmi
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@ -526,10 +544,31 @@ static const int features_indices[] = {
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rtm
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avx512f
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avx512dq
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rdseed
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avx512ifma
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avx512pf
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avx512er
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avx512cd
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sha
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avx512bw
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avx512vl
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*/
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static const char features_string[] =
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" sse3\0"
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" sse2\0"
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" avx512vbmi\0"
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" ssse3\0"
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" fma\0"
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" cmpxchg16b\0"
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@ -546,15 +585,27 @@ static const char features_string[] =
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" avx2\0"
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" bmi2\0"
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" rtm\0"
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" avx512f\0"
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" avx512dq\0"
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" rdseed\0"
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" avx512ifma\0"
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" avx512pf\0"
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" avx512er\0"
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" avx512cd\0"
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" sha\0"
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" avx512bw\0"
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" avx512vl\0"
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"\0";
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static const quint8 features_indices[] = {
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0, 6, 5, 5, 5, 5, 5, 5,
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5, 12, 5, 5, 19, 24, 5, 5,
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5, 5, 5, 36, 44, 5, 52, 59,
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5, 67, 5, 5, 72, 77, 83, 5,
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5, 5, 5, 91, 96, 101, 5, 5,
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107, 5, 5, 113
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0, 6, 12, 5, 5, 5, 5, 5,
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5, 24, 5, 5, 31, 36, 5, 5,
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5, 5, 5, 48, 56, 5, 64, 71,
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5, 79, 5, 5, 84, 89, 95, 5,
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5, 5, 5, 103, 108, 113, 5, 5,
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119, 5, 5, 125, 5, 5, 5, 5,
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130, 139, 149, 5, 5, 157, 5, 5,
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5, 5, 169, 179, 189, 199, 204, 214
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};
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#else
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static const char features_string[] = "";
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@ -218,6 +218,23 @@
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# endif
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#endif
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#define QT_FUNCTION_TARGET_STRING_AVX512F "avx512f"
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#define QT_FUNCTION_TARGET_STRING_AVX512CD "avx512cd"
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#define QT_FUNCTION_TARGET_STRING_AVX512ER "avx512er"
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#define QT_FUNCTION_TARGET_STRING_AVX512PF "avx512pf"
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#define QT_FUNCTION_TARGET_STRING_AVX512BW "avx512bw"
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#define QT_FUNCTION_TARGET_STRING_AVX512DQ "avx512dq"
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#define QT_FUNCTION_TARGET_STRING_AVX512VL "avx512vl"
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#define QT_FUNCTION_TARGET_STRING_AVX512IFMA "avx512ifma"
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#define QT_FUNCTION_TARGET_STRING_AVX512VBMI "avx512vbmi"
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#define QT_FUNCTION_TARGET_STRING_F16C "f16c"
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#define QT_FUNCTION_TARGET_STRING_RDRAND "rdrnd"
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#define QT_FUNCTION_TARGET_STRING_BMI "bmi"
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#define QT_FUNCTION_TARGET_STRING_BMI2 "bmi2"
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#define QT_FUNCTION_TARGET_STRING_RDSEED "rdseed"
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#define QT_FUNCTION_TARGET_STRING_SHA "sha"
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// other x86 intrinsics
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#if defined(Q_PROCESSOR_X86) && ((defined(Q_CC_GNU) && (Q_CC_GNU >= 404)) \
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|| (defined(Q_CC_CLANG) && (Q_CC_CLANG >= 208)) \
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@ -260,23 +277,97 @@ enum CPUFeatures {
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CpuFeatureSSSE3 = (0 + 9),
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CpuFeatureSSE4_1 = (0 + 19),
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CpuFeatureSSE4_2 = (0 + 20),
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CpuFeatureMOVBE = (0 + 22),
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CpuFeaturePOPCNT = (0 + 23),
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CpuFeatureAES = (0 + 25),
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CpuFeatureAVX = (0 + 28),
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CpuFeatureF16C = (0 + 29),
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CpuFeatureRDRAND = (0 + 30),
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// 31 is always zero and we've used it for the QSimdInitialized
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// in level 7, leaf 0, EBX
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CpuFeatureBMI = (32 + 3),
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CpuFeatureHLE = (32 + 4),
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CpuFeatureAVX2 = (32 + 5),
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CpuFeatureBMI2 = (32 + 8),
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CpuFeatureRTM = (32 + 11),
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CpuFeatureAVX512F = (32 + 16),
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CpuFeatureAVX512DQ = (32 + 17),
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CpuFeatureRDSEED = (32 + 18),
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CpuFeatureAVX512IFMA = (32 + 21),
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CpuFeatureAVX512PF = (32 + 26),
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CpuFeatureAVX512ER = (32 + 27),
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CpuFeatureAVX512CD = (32 + 28),
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CpuFeatureSHA = (32 + 29),
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CpuFeatureAVX512BW = (32 + 30),
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CpuFeatureAVX512VL = (32 + 31),
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// in level 7, leaf 0, ECX (out of order, for now)
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CpuFeatureAVX512VBMI = 2, // uses the bit for DTES64
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#endif
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// used only to indicate that the CPU detection was initialised
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QSimdInitialized = 0x80000000
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};
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static const uint qCompilerCpuFeatures = 0
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static const quint64 qCompilerCpuFeatures = 0
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#if defined __SHA__
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| (Q_UINT64_C(1) << CpuFeatureSHA)
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#endif
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#if defined __AES__
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| (Q_UINT64_C(1) << CpuFeatureAES)
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#endif
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#if defined __RTM__
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| (Q_UINT64_C(1) << CpuFeatureRTM)
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#endif
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#ifdef __RDRND__
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| (Q_UINT64_C(1) << CpuFeatureRDRAND)
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#endif
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#ifdef __RDSEED__
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| (Q_UINT64_C(1) << CpuFeatureRDSEED)
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#endif
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#if defined __BMI__
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| (Q_UINT64_C(1) << CpuFeatureBMI)
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#endif
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#if defined __BMI2__
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| (Q_UINT64_C(1) << CpuFeatureBMI2)
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#endif
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#if defined __F16C__
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| (Q_UINT64_C(1) << CpuFeatureF16C)
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#endif
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#if defined __POPCNT__
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| (Q_UINT64_C(1) << CpuFeaturePOPCNT)
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#endif
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#if defined __MOVBE__ // GCC and Clang don't seem to define this
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| (Q_UINT64_C(1) << CpuFeatureMOVBE)
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#endif
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#if defined __AVX512F__
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| (Q_UINT64_C(1) << CpuFeatureAVX512F)
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#endif
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#if defined __AVX512CD__
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| (Q_UINT64_C(1) << CpuFeatureAVX512CD)
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#endif
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#if defined __AVX512ER__
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| (Q_UINT64_C(1) << CpuFeatureAVX512ER)
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#endif
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#if defined __AVX512PF__
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| (Q_UINT64_C(1) << CpuFeatureAVX512PF)
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#endif
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#if defined __AVX512BW__
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| (Q_UINT64_C(1) << CpuFeatureAVX512BW)
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#endif
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#if defined __AVX512DQ__
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| (Q_UINT64_C(1) << CpuFeatureAVX512DQ)
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#endif
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#if defined __AVX512VL__
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| (Q_UINT64_C(1) << CpuFeatureAVX512VL)
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#endif
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#if defined __AVX512IFMA__
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| (Q_UINT64_C(1) << CpuFeatureAVX512IFMA)
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#endif
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#if defined __AVX512VBMI__
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| (Q_UINT64_C(1) << CpuFeatureAVX512VBMI)
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#endif
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#if defined __AVX2__
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| (Q_UINT64_C(1) << CpuFeatureAVX2)
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#endif
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