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deps: cherry-pick 2e4da65 from v8's 4.8 upstream

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Float v8 patch, which has been committed to v8 master and
backported to 4.8 and 4.9 in google repos, onto 4.8 v8 in
deps to resolve https://github.com/nodejs/node/issues/5089

Original title/commit from google repos for 4.8 is:
 PPC: [turbofan] Support for CPU models lacking isel.
 2e4da65332

PR-URL: https://github.com/nodejs/node/pull/5293
Fixes: https://github.com/nodejs/node/issues/5089
Reviewed-By: Ben Noordhuis <info@bnoordhuis.nl>
Reviewed-By: jbergstroem - Johan Bergström <bugs@bergstroem.nu>
This commit is contained in:
Michael Dawson 2016-02-17 17:18:00 -05:00
parent db9128135f
commit ff0d339324
1 changed files with 31 additions and 31 deletions
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54
deps/v8/src/compiler/ppc/code-generator-ppc.cc vendored
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@ -1313,8 +1313,8 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
PPCOperandConverter i(this, instr); PPCOperandConverter i(this, instr);
Label done; Label done;
ArchOpcode op = instr->arch_opcode(); ArchOpcode op = instr->arch_opcode();
bool check_unordered = (op == kPPC_CmpDouble);
CRegister cr = cr0; CRegister cr = cr0;
int reg_value = -1;
// Overflow checked for add/sub only. // Overflow checked for add/sub only.
DCHECK((condition != kOverflow && condition != kNotOverflow) || DCHECK((condition != kOverflow && condition != kNotOverflow) ||
@ -1326,45 +1326,45 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
Register reg = i.OutputRegister(instr->OutputCount() - 1); Register reg = i.OutputRegister(instr->OutputCount() - 1);
Condition cond = FlagsConditionToCondition(condition); Condition cond = FlagsConditionToCondition(condition);
if (op == kPPC_CmpDouble) {
// check for unordered if necessary
if (cond == le) {
reg_value = 0;
__ li(reg, Operand::Zero());
__ bunordered(&done, cr);
} else if (cond == gt) {
reg_value = 1;
__ li(reg, Operand(1));
__ bunordered(&done, cr);
}
// Unnecessary for eq/lt & ne/ge since only FU bit will be set.
}
if (CpuFeatures::IsSupported(ISELECT)) {
switch (cond) { switch (cond) {
case eq: case eq:
case lt: case lt:
__ li(reg, Operand::Zero()); case gt:
__ li(kScratchReg, Operand(1)); if (reg_value != 1) __ li(reg, Operand(1));
__ isel(cond, reg, kScratchReg, reg, cr); __ li(kScratchReg, Operand::Zero());
__ isel(cond, reg, reg, kScratchReg, cr);
break; break;
case ne: case ne:
case ge: case ge:
__ li(reg, Operand(1));
__ isel(NegateCondition(cond), reg, r0, reg, cr);
break;
case gt:
if (check_unordered) {
__ li(reg, Operand(1));
__ li(kScratchReg, Operand::Zero());
__ bunordered(&done, cr);
__ isel(cond, reg, reg, kScratchReg, cr);
} else {
__ li(reg, Operand::Zero());
__ li(kScratchReg, Operand(1));
__ isel(cond, reg, kScratchReg, reg, cr);
}
break;
case le: case le:
if (check_unordered) { if (reg_value != 1) __ li(reg, Operand(1));
__ li(reg, Operand::Zero()); // r0 implies logical zero in this form
__ li(kScratchReg, Operand(1));
__ bunordered(&done, cr);
__ isel(NegateCondition(cond), reg, r0, kScratchReg, cr);
} else {
__ li(reg, Operand(1));
__ isel(NegateCondition(cond), reg, r0, reg, cr); __ isel(NegateCondition(cond), reg, r0, reg, cr);
}
break; break;
default: default:
UNREACHABLE(); UNREACHABLE();
break; break;
} }
} else {
if (reg_value != 0) __ li(reg, Operand::Zero());
__ b(NegateCondition(cond), &done, cr);
__ li(reg, Operand(1));
}
__ bind(&done); __ bind(&done);
} }